Sony Corporation

Sony Semiconductor Solutions Corporation

Daisuke Yoshioka

Toshiyuki Nishihara

Takeshi Ishimoto

Hiroaki Ebihara

Youji Sakioka

Kazuhide Namba

Ryota Moriwaka

Hidetoshi Yamanaka

Koji Sakui

Kazuhiro Suzuki

Shigeru Atsumi

Jun Sumino

Shiro Omori

Masayuki Tachi

Toru Nishi

Taro Sugizaki

Go Yamanaka

Norihiro Ichimaru

Kazuhide Fujita

Hiroshi Kawanobe

Kazuhito Kobayashi

Naoki Hosoi

Yousuke Horie

Shoyu Tanaka

Katsushi Uchiyama

Kazuto Kamimura

Toshiyuki Nishimura

Takeshi Kozasa

Takesi Kozasa

Keneki Go

Naoto Hayashida

The present disclosure relates to a solid-state imaging device that makes it possible to suppress deterioration of phase difference information, and an electronic device. There is provided a solid-state imaging device including a pixel array unit in which a plurality of pixels is two-dimensionally arrayed. The plurality of pixels includes a phase difference pixel for phase difference detection, the pixel array unit has an array pattern in which pixel units including neighboring pixels of a same color are regularly arrayed, and the phase difference pixel is partially not added when horizontal/vertical addition is performed on a pixel signal of a predetermined pixel in a horizontal direction and a pixel signal of a predetermined pixel in a vertical direction, in reading the plurality of pixels. The present disclosure can be applied to, for example, a CMOS image sensor having a phase difference pixel.

Solid-state imaging device and electronic device

The present technology relates to a solid-state image sensor, an imaging control method, a signal processing method, and an electronic apparatus that suppress the deterioration of image quality, which is caused by the difference of sensitivity between pixels. A solid-state image sensor includes: a pixel array unit including a plurality of pixels arranged, the plurality of pixels including a plurality of kinds of pixels, the plurality of kinds of pixels including a first pixel and a second pixel, the first pixel having the highest sensitivity, the second pixel having a sensitivity lower than the sensitivity of the first pixel; and a control unit that controls at least one of an analog gain and exposure time of/for the respective pixels depending on a ratio between the sensitivities of the first pixel and the second pixel. The present technology is applicable to a solid-state image sensor such as a CMOS image sensor.

Solid-state image sensor, imaging control method, signal processing method, and electronic apparatus

An imaging device includes an exposure control unit, a determination unit, and an illuminance calculation unit. The exposure control unit is configured to control a plurality of exposure times. The determination unit is configured to determine whether or not saturation occurs using at least one data item of a plurality of data items obtained during the plurality of exposure times. The illuminance calculation unit is configured to calculate, if the determination unit determines that the saturation occurs, an illuminance using a data item different from the at least one data item used in the determination.

Imaging device and imaging method having an illuminance calculation unit calculating respective illuminances corresponding to digital signals

Imaging device and imaging method having saturation determination for an illuminance calculation

A solid-state imaging device includes: a pixel unit in which pixels that perform photoelectric conversion are arranged in an optical black region and a valid pixel region; a readout processing unit that applies, to a readout signal of the pixel unit, readout processing corresponding to a reference signal subjected to clamp processing; and a clamp processing unit that clamps, referring to a readout signal level in the optical black region, a reference signal in the valid pixel region with an acquired clamp value, which is a value with which the signal level is reduced to zero. The clamp processing unit acquires, when information concerning readout is changed, a clamp value predicted from the clamp value before the change and a ratio of charge accumulation times before and after the change, and the readout processing unit performs first signal readout processing after the change with a reference signal clamped by the predicted clamp value.

Solid-state imaging device and camera system which performs clamp processing

A nonvolatile semiconductor storage device and method of managing the same are provided. The nonvolatile semiconductor storage device includes a nonvolatile memory configured to be electrically rewritable; and a controller configured to control an access area of the nonvolatile memory on the basis of information associated with management of the nonvolatile memory. The controller partitions an area of the nonvolatile memory for management and numbers management information for managing data for each area and a map of the management information in an integrated manner to write the numbered management information and map to the nonvolatile memory, thereby determining whether the management information and the map are normal on the basis of the numbering.

Nonvolatile semiconductor storage device and method of managing the same

A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.

Storage device, computer system, and data writing method

A nonvolatile memory system includes a nonvolatile memory and a controller. The controller is configured to manage the nonvolatile memory based on management information. The management information of the controller includes a basic table for collectively managing a plurality of blocks and differential information between the blocks. The controller is operable to manage the blocks collectively with the basic table and manage different portions of the blocks within the collected range using the differential information.

Nonvolatile memory system and management method for nonvolatile memory

A storage device that includes: a flash memory device being a main storage medium; a cache memory for use for the flash memory device; and a control circuit. In the storage device, based on a write command and address information provided from outside, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.

A memory system including a nonvolatile semiconductor storage device includes: a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and a control unit. The control unit sequentially selects logical block addresses in the second data area in which data is hardly rewritten and updates physical block addresses at new rewriting destinations in the first data area in which data is frequently rewritten to physical block addresses corresponding to the logical block addresses selected.

Nonvolatile memory with active and passive wear leveling

A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.

Semiconductor memory device and signal processing system

A semiconductor memory device using inexpensive block access semiconductor memories for storage media and able to be treated like a usual randomly accessible system memory, including a first semiconductor memory and a second semiconductor memory, wherein the second semiconductor memory is a cache of the first semiconductor memory, the first semiconductor memory is accessed via the second semiconductor memory, there are a first address region and a second address region on logical memory addresses accessed from the outside, at least part of the second semiconductor memory is mapped to the first address region, and a function of controlling data transfer between the first semiconductor memory and the second semiconductor memory by accessing the second address region is provided, and an access method and a memory control system of the same.

Semiconductor memory device and access method and memory control system for same

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Kanagawa, Japan

Daisuke Yoshioka