Renesas Electronics Corporation

Renesas Technology Corp.

Ricoh Company, Ltd.

Floadia Corporation

Mitsubishi Electric Corporation

Daisuke Okada

Digh Hisamoto

Kan Yasui

Tsutomu Okazaki

Toshihiro Tanaka

Akira Kato

Yasushi Ishii

Tetsuya Ishimaru

Toshikazu Matsui

Kyoya Nitta

Tsuyoshi Arigane

Hideaki Matsui

Shinichiro Kimura

Takeshi Fujita

Shoji Yoshida

Fukuo Owada

Kazumasa Yanagisawa

Yasuhiro Taniguchi

Shinji Yoshida

Yoshihiro Ikeda

Yasuhiko Kawashima

Yasuhiro Shimamoto

Hiroji Ozaki

Motoi Ashida

Yutaka Shinagawa

Jun Yoshida

Kozo Katayama

Takashi Yamaki

Kosuke Okuyama

Hideaki Yamakoshi

Yasuyuki Igarashi

Yuka Saito

Shoji Shukuri

Sadao Takahashi

Shinichiro Abe

Takaharu Ueda

Kenji Shiraishi

Soichiro Yokota

Masahiro Hayashi

Keisuke Nakazawa

Hiroshi Kigawa

Yuto Shibata

Nobuhiro Shindo

Keisuke Tsukamoto

Hajime Kubota

Kenichi Akita

Keisuke Kuwahara

Naruhiko Ogasawara

Seiji Muranaka

Keisuke Iwasa

Naohiko Kubo

Takuo Kugiya

Tsuyoshi Koga

Hiroki Kubozono

Tatsuya Fukumura

Seiya Amano

Kazuma Saito

Hiroshi Yanagita

Saori Iura

Masateru Kumagai

Tabito Suzuki

Kazuma Saitoh

Sukehiro Kimura

Yasufumi Morimoto

Yohichiroh Ohbayashi

Naohiro Hosoda

Hiroya Uruta

Koji Kishi

Noboru Tamura

Yuu Yamada

Masaya Sakai

Naoyuki Maruyama

Nobuyuki Iwata

Keiichi Haraguchi

Akiko Kitayama

Shintaroh Kida

Chan Gu

Yasafumi Morimoto

Takeo Momose

Kazuharu Yamabe

Toshio Kudo

Hirosi Kigawa

According to an aspect of the present invention, an information processing apparatus includes an object region detecting unit, a local region detecting unit, an object specifying unit. The object region detecting unit is configured to detect an object region based on one of distance information and luminance information. The local region detecting unit is configured to, when a divided area obtained by dividing the detected object region meets a predetermined condition, detect the divided area as a local region. The object specifying unit is configured to specify, as a specification target object, the object region in which the local region is continuously detected.

Information processing apparatus, imaging apparatus, apparatus control system, movable object, information processing method, and computer-readable recording medium

An information processing device includes an image analyzing unit. The image analyzing unit includes an object region setting unit configured to set an object region, for image information obtained by capturing an imaging range, the object region corresponding to an object existing in the imaging range; a luminance information acquiring unit configured to acquire luminance information indicating luminance in the imaging range; and a correcting unit configured to correct the object region based on the luminance information in a luminance detection region set in a lower part of the object region.

Information processing device, imaging device, apparatus control system, movable body, information processing method, and computer program product

When a memory cell (MC) is downsized by reducing the distance between a drain region () and a source region () on the surface of a fin (S) with a high impurity concentration inside the fin (S), the shape of the fin (S) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device

A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Semiconductor device

A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.

Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device

A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.

Semiconductor device and manufacturing method of semiconductor device

An information processing system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus includes an acquisition part creating a first information request, a first transmitter transmitting the first information request to the second information processing apparatus, a first receiver receiving the first information from the second information processing apparatus, a display controller controlling displaying the first information, and a first storage storing second information, the display controller controlling displaying the second information when the second information is stored in the first storage. The second information processing apparatus includes a second storage storing the first information, a second receiver receiving the first information request, an extracting part extracting the first information from the second storage in response to the first information request, and a second transmitter transmitting the first information to the first information processing apparatus.

Information processing system, information processing apparatus, information processing method, and recording medium

A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

Semiconductor device and method of driving semiconductor device

A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.

Semiconductor device and method of manufacturing the same

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Tokyo, Japan

Daisuke Okada