Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Shimadzu Corporation

Victor Company of Japan, Limited

Panasonic Corporaton

Daisuke Murakami

Yuji Takai

Takahide Baba

Isao Kawamoto

Yoshiharu Watanabe

Koki Yoshida

Seiji Horii

Dai Hirose

Yuki Soga

Toshihiro Fukuyama

Yasuaki Watanabe

Tetsuji Kishi

Yuichi Ikemura

Yukio Okabe

Katsuhiro Masuo

Mitsuru Umeda

Mitsuru Hayakawa

Yasuhiro Fujita

Yasuo Nishioka

Taku Ogawa

An X-ray fluoroscopic imaging apparatus includes an operation element that includes a motion axis selection switch and a plurality of direction switches; and a control element that controls a shifting of a relative location between an imaging element and a table relative to a motion-axis by the motion-axis selection switch to a shiftable predetermined motion-axis mode.

X-ray fluoroscopic imaging apparatus

An X-ray imaging apparatus includes an X-ray irradiation region adjustment unit for adjusting an X-ray irradiation region and a control unit for controlling the X-ray irradiation region adjustment unit so as to adjust the X-ray irradiation region based on a set region of interest in the case of a region of interest highlighting mode that highlights a predetermined target object within the region of interest set in the image generated by the image processing unit.

X-ray imaging apparatus

An X-ray photography device capable of visualizing the operating state or position of a support unit in an image system during examinations with memory switches and enhancing the operability of the memory switches is provided. When a plurality of memory switches-is operated, target rotation information corresponding to the memory switches are read from a target rotation information memory unit, and a C-arm is controlled to rotate, so as to make actual rotation information consistent with the target rotation information. The memory switches-are respectively arranged in association with rotation directions and rotation angles to designate specific storage areas in the target rotation information memory unitcorresponding to the directions and angles. During the rotation control or when the actual rotation information is consistent with the target rotation information, the corresponding display lamp (one of display lamps-) of the operated memory switch is turned on.

X-ray photography system

A delay circuit of the present disclosure includes a first delay unit and a second delay unit which are connected in series and delay an input signal to generate a delayed signal. The first delay unit includes a first signaling pathway, and changes, based on a first delay control value, a first amount of delay to be provided to the input signal by switching signaling pathways for transmitting the input signal that are within the first pathway. The second delay unit includes a second signaling pathway, and changes, based on a second delay control value, a second amount of delay to be provided to the input signal without switching the second signaling pathway for transmitting the input signal.

Delay circuit, delay controller, memory controller, and information terminal

Before arbitration is performed in an arbitration section, an access from a master is kept in a waiting state until update of a conversion table buffer is performed, and an address conversion section is provided in a subsequent stage of the arbitration section. Without waiting for the completion of buffer update, an access is issued in advance at a time when it is assured that update is completed at the completion of address conversion. Thus, influences of waiting buffer update on another master can be eliminated and access latency can be reduced.

Data processing system

An access stop control apparatus is provided in a resource control apparatus so that reception of access from a master apparatus is temporarily stopped during changing of a clock frequency and the clock frequency is changed at safe timing. Thereby, the operation of the master apparatus does not need to be stopped during changing of the clock frequency and a period for which access to a resource is stopped can be suppressed. Therefore, execution of an application requiring real-timeness is not affected.

Data processing apparatus

A clock enable (CKE) control circuit () is provided between a memory control circuit () and a SDRAM (). When a system is in, e.g., a sleep state, the CKE control circuit () controls a CKE signal outputted to the SDRAM () such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (), while maintaining the low-power-consumption mode of the SDRAM (), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (), while maintaining the low-power-consumption mode of the SDRAM ().

Memory control device

A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave.

System and method for bus transmission cancellation

An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.

Resource management device

A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.

Resource management device for managing access from bus masters to shared resources

A variable frequency oscillator comprises an oscillating loop and a variable phase shifter for imparting one of two different phase shifts depending upon the polarities of a DC control voltage to a signal from the oscillating loop. The phase-shifted signal has its amplitude controlled by the amplitude of the control voltage and is combined with the signal in the oscillating loop. The vector sum of the combined signals determines the phase angle of the oscillator signal and hence the frequency thereof.

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Kyoto, Japan

Daisuke Murakami