Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Daisuke Miyashita

Jun Deguchi

Shouhei Kousai

Fumihiko Tachibana

Junji Wadatsumi

Asuka Maki

Yuji Satoh

Makoto Morimoto

Yuta Tsubouchi

Radu Berdan

Kengo Nakata

Hiroyuki Kobayashi

Atsushi Kawasumi

Osamu Torii

Riki Suzuki

Toshimasa Namekawa

Kohei Oikawa

Shinji Miyano

Hidehiro Shiga

Ryo Yamaki

Mototsugu Hamada

Naoaki Kokubun

Shinichi Sasaki

Takashi Toi

Yusuke Niki

Hideyuki Kokatsu

Hiroki Ishikuro

Yasuto Hoshi

According to one embodiment, an arithmetic apparatus includes a non-volatile first memory, a second memory, and a controller. The first memory stores a model to be trained. The second memory has a smaller storage capacity than the first memory. The controller executes learning processing that updates a first parameter of the model based on a loss value obtained by inputting training data into the model stored in the first memory, and stores cumulative update information indicating a difference of the first parameter before and after the update in the second memory. In addition, the controller executes the learning processing using a second parameter in which the cumulative update information stored in the second memory is reflected in the first parameter read from the model stored in the first memory, and stores a difference between a third parameter obtained by updating the second parameter and the first parameter, in the second memory as the cumulative update information.

Arithmetic apparatus and arithmetic method

According to one embodiment, an information processing method includes: calculating a first feature amount of query data in a first field; calculating first similarity degrees between the first feature amount and second feature amounts in the first field; obtaining, based on the first similarity degrees, third feature amounts in a second field that are associated with feature amounts selected from the second feature amounts, the second field being different from the first field; calculating fourth feature amounts in the second field, for choices concerning the query data; calculating second similarity degrees between the third feature amounts and the fourth feature amounts; and selecting, based on the second similarity degrees, an answer to the query data among answer candidates corresponding to the third feature amounts.

Information processing method, information processing device, and computer system

According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.

Semiconductor integrated circuit and arithmetic system

According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

Computation system with a plurality of comparators and a global circuit

A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

Semiconductor storage device

An arithmetic apparatus used for a neural network includes a plurality of digital-time conversion circuits connected in series and a time-digital conversion circuit connected to a last digital-time conversion circuit in the series. Each of the digital-time conversion circuits is configured to delay a first input time signal by a variable amount, delay a second input time signal by a fixed amount, and output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with the input data. The time-digital conversion circuit is configured to generate a digital output signal by comparing first and second output time signals from the last digital-time conversion circuit.

Arithmetic apparatus for a neural network

An arithmetic operation device is provided that removes a part of parameters of a predetermined number of parameters from a first machine learning model which includes the predetermined number of parameters and is trained so as to output second data corresponding to input first data, determines the number of bits of a weight parameter according to required performance related to an inference to generate a second machine learning model, and acquires data output from the second machine learning model so as to correspond to the input first data with a smaller computational complexity than the first machine learning model.

Arithmetic operation device using a machine learning model, arithmetic operation method using a machine learning model, and training method of the machine learning model

According to one embodiment, an information processing device includes: an encoder including a first layer and a second layer which are coupled in series; and a decoder. The encoder is configured to: generate, based on first data, a first key and a first value in the first layer, and a second key and a second value in the second layer; and generate, based on second data different from the first data, a first query in the first layer, and a second query in the second layer. The decoder is configured to: generate third data which is included in the first data and is not included in the second data, based on the first key, the first value, the first query, the second key, the second value, and the second query.

Information processing device, information processing method, and generating method of learning model

According to one embodiment, an information processing method includes performing, in an intermediate layer of a deep neural network, a forward propagation using a first parameter and based on a first input value represented by a first bit number; performing quantization to produce a second input value represented by a second bit number smaller than the first bit number, and storing the produced second input value in the memory; calculating a second parameter based on a result of an operation using the second input value stored in the memory and a value obtained by the forward propagation, the second parameter being an update of the first parameter and for use in the learning process; and determining a condition for the quantization based on a gradient difference obtained in said calculating the second parameter.

Information processing method and information processing apparatus

According to one embodiment, a processing device includes: a first circuit configured to execute first processing using a first matrix to first data of a size of 5&#xd7;5 within input data to generate second data; a second circuit configured to execute second processing using a second matrix to third data of a size of 3&#xd7;3 to generate fourth data; a third circuit configured to execute a product-sum operation on the second data and the fourth data; and a fourth circuit configured to execute third processing using a third matrix on a result of the product-sum operation on the second data and the fourth data to obtain a first value corresponding to a result of a product-sum operation on the first data and the third data.

Processing device of a neural network to process image data

According to one embodiment, a semiconductor memory device includes a memory, a controller, and a sense amplifier. The memory includes a plurality of memory cells, wherein each of the memory cells can store a multi level indicating one data. The controller writes the multi level to one cell of the memory. The sense amplifier performs unary read of data from the multi level written in the one cell. The data is data in which an error of a predetermined lower significant bit is allowed. The controller reads data indicated by the multi level stored in the one cell of the memory from the sense amplifier.

Semiconductor memory device

According to an embodiment, there is provided a semiconductor device including a plurality of operation circuits each including a multiplier including a first input terminal and a second input terminal and configured to calculate a product of a value input via the first input terminal and a value input via the second input terminal, and an accumulator configured to integrate an output of the multiplier and output an integrated value that is obtained by integrating output values of the multiplier. The plurality of operation circuits are divided into groups by two manners, where by the first manner multiple operation circuits are configured to receive a common first value via the respective first input terminals, and by the second manner multiple operation circuits are configured to receive a common second value via the respective second input terminals.

Semiconductor device having plural operation circuits including multiplier and accumulator

According to one embodiment, in a reception apparatus, a reception node is capable of being connected to a wired communication channel. A first frequency conversion circuit is electrically connected to the reception node. A second frequency conversion circuit is electrically connected to the reception node. A first adder circuit is electrically connected to the first frequency conversion circuit. A second adder circuit is electrically connected to the second frequency conversion circuit. A first correction circuit is electrically connected between the first frequency conversion circuit and the second adder circuit. A second correction circuit is electrically connected between the second frequency conversion circuit and the first adder circuit. The first correction circuit includes a reverse phase amplifier and a first capacitative element. The second correction circuit includes a positive phase amplifier and a second capacitative element.

Reception apparatus, transmission apparatus, and communication system

According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.

Transmitter and receiver

According to one embodiment, a semiconductor memory device includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, a first bus, an operation controller circuit, and a second bus. The read circuit array reads the data from the nonvolatile memory. The multiply-accumulate operator array receives the data read from the read circuit array. The first bus is connected between the read circuit array and the multiply-accumulate operator array and having a first bit width. The operation controller circuit is electrically connected to the multiply-accumulate operator array. The second bus is connected to the operation controller circuit and having a second bit width smaller than the first bit width.

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Kawasaki, Japan

Daisuke Miyashita