Fujitsu Corporation

Fujitsu Semiconductor Limited

Daisuke Miura

Kenji Yoshida

Shuji Yoshida

Masayuki Okamoto

Toshio Arakawa

Mitsuaki Nagasaka

Hiroyuki Honda

Junichi Shikatani

Shinji Oyamada

A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops.

Semiconductor device

In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.

LSI layout method and apparatus for cell arrangement in which timing is prioritized

Each binary carry logic circuit of half adder circuits other than that for the least significant digit comprises a transfer gate turned on when an input bit A is active and receiving a carry-in bit *C at its data input, and a transistor , turned on when the input bit A is inactive, connected between a power supply potential VDD and the data output of the transfer gate a signal on which is a carry-out bit *C . Transfer gates to of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A to A , letting the carry-in bit *C from the least significant digit propagate through the transfer gate chain at a high speed.

Logic circuit for fast carry/borrow

Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S ) sorting the terminals according to the width thereof; and (S S ) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal. In another embodiment, the method comprises the steps of (a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and (b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.

Method and apparatus for automatic wiring design between block circuits of integrated circuit

A partial random access memory includes a plurality of memory cells arrayed in matrix form, a plurality of pairs of bit lines extending in a column direction, each of the plurality of memory cells being coupled to corresponding one of pairs of bit lines, and a plurality of word lines including a plurality of first and second word lines. One first word line and one second word line are paired and arranged on both sides of an arrangement of the memory cells in a row direction. Each of the plurality of memory cells is connected to at least one of the first and second word lines. An activating circuit coupled to the plurality of word lines separately activates the first and second word lines, depending on an address signal supplied from an external circuit, thereby independently selecting the first and second word lines. An input/output circuit coupled to the plurality of bit lines writes input data into corresponding memory cells and reads out output data from corresponding memory cells.

Partial random access memory

A master slice type semiconductor integrated circuit which includes a semiconductor chip, input/output cells arranged in a peripheral portion of the semiconductor chip, and basic cells arranged in an entire central portion of the semiconductor chip excluding the peripheral portion of the semiconductor chip. Each of the basic cells are formed by a complementary metal oxide semiconductor (MOS) forming part and an N-channel metal oxide semiconductor (NMOS) forming part. The CMOS forming part forms a CMOS by employing same number of P-channel metal oxide semiconductor (PMOS) transistors and NMOS transistors, while the NMOS forming part forms a plurality of NMOS transistors on at least one end of the CMOS forming part in a direction parallel to the CMOS forming part.

Growing community of inventors

Yokohama, Japan

Daisuke Miura