Kabushiki Kaisha Toshiba

Daisuke Kato

Yohji Watanabe

Daisaburo Takashima

Yukihito Oowaki

Munehiro Yoshida

Takashi Taira

Yasuyuki Kajitani

Kenji Ishizuka

Eiichi Makino

Yutaka Shirai

A semiconductor memory device including a memory cell array which has a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs which transfer data among the memory cells, a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers including a plurality of sense amplifier circuits, and the plurality of sense amplifier circuits being connected respectively to the plurality of bit line pairs to amplify data transferred to the bit line pairs, a plurality of word lines connected to the memory cells, a plurality of wirings disposed respectively corresponding to the plurality of word lines and above the plurality of word lines, and a plurality of stitch portions which connect the plurality of word lines to the plurality of wirings every predetermined intervals. Two active areas in which the sense amplifier circuit is formed respectively in both sides of a stitch area corresponding to each of the stitch portions in the sense amplifier bank are connected to each other, and a dummy transistor is disposed on the connected active areas.

Semiconductor memory device

A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.

A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.

Semiconductor storage device formed to optimize test technique and redundancy technology

There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair regions as a group of first/second normal elements with permission of replacement by each first/second redundant element.

A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.

Semiconductor memory device having redundancy system

A sense amplifier section of a semiconductor memory device includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to or from the memory cell array via the bit line pairs. The sense amplifier section includes an array of layout units respectively including circuit portions of sense amplifiers, wherein the layout units are disposed in the array of layout units at intervals smaller than intervals of the bit line pairs.

Sense amplifier control circuit of semiconductor memory device

A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair region as group of first/second normal elements with permission of replacement by each first/second redundant element.

A semiconductor integrated circuit includes a plurality of functional circuits, a plurality of signal transmission lines disposed to interconnect among the functional circuits for transfer of a plurality of control signals which are to be supplied to respective functional circuits and are different in timing from one another, and a control circuit for generation of the control signals. The control circuit has a plurality of stages of control signal generator circuits that generate and issue the control signals respectively. The control signal generator circuits are specifically linked together so that when one generator circuit at a certain stage generates at its output a control signal to be transferred over a corresponding signal line, another circuit at the next stage is activated in response to receipt of this control signal.

Semiconductor integrated circuit device

A sense amplifier control circuit for use in a semiconductor memory device is provided which comprises a sense amplifier comprising first transistors of a first conductivity type connected in the form of a latch type differential amplifier, a set driver corresponding to the sense amplifier and the set driver comprising a second transistor of a second conductivity type for connecting the common source line of the latch type differential amplifier to a restore power supply line.

A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.

Semiconductor integrated circuit device having fuses and fuse latch circuits

In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.

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Kamakura, Japan

Daisuke Kato