Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Daisuke Iwahashi

Takeshi Tanaka

Keiichi Kurokawa

Naoki Yoshimatsu

Hiroshi Amano

Tokuzo Kiyohara

Masayoshi Tojima

Hiroki Monta

Hideyuki Kanzaki

Rumi Ohnishi

Takao Hasegawa

A control method according to the present disclosure includes: obtaining (receiving) position information (a danger warning signal) indicating a target position where a target object is present; determining whether the vehicle is driving autonomously or is being driven manually; when the vehicle is determined to be being driven manually, inspecting whether the target position is located within a predetermined region of a travel route of the vehicle based on the position information; when the target position is located within the predetermined region, changing the light transmission state of the headlight from a first state to a second state; and when the vehicle is determined to be driving autonomously and/or the target position is not located within the predetermined region, maintaining the light transmission state of the headlight.

Control method and control device

A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.

Resource request arbitration device, resource request arbitration system, resource request arbitration method, integrated circuit, and program

An image decoding device for increasing decoding efficiency and reducing the number of memory accesses includes a division unit dividing a picture into first and second coded image data; and first and second decoding units decoding, in parallel, the first and second coded image data and storing decoding results into a frame storage unit. The first and second decoding units decode the first and second coded image data using second and first decoding result information, respectively, and store the resulting first and second decoding result information into an information storage unit. When decoding a target macroblock, each of the first and second decoding units performs image processing on the corresponding second or first decoding result information indicating part of the decoded macroblock included in the macroblock line adjacent to the macroblock line including the target macroblock, and the target macroblock.

Image decoding device, image coding device, methods thereof, programs thereof, integrated circuits thereof, and transcoding device

An image decoding device which increases decoding efficiency and can be easily implemented includes: a division unit dividing coded image data into first and second coded image data; a frame storage unit; first and second decoding units decoding, in parallel, the first and second coded image data; and an information storage unit. The first decoding unit decodes the first coded image data using second decoding result information stored in the information storage unit and stores, as first decoding result information, a part of information generated by the decoding into the information storage unit. The second decoding unit decodes the second coded image data using the first decoding result information stored in the information storage unit and stores, as the second decoding result information, a part of information generated by the decoding into the information storage unit.

In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO block is determined, placement of the IO block is determined such that the IO block is placed close to the external terminal to alleviate constraints on the wiring between the IO block and the external terminal, and timing adjustment circuits whose number is determined according to the wiring length of a bus (or a shared bus) connecting a data transfer circuit and the IO block is inserted into the bus.

Integrated circuit manufacturing method and semiconductor integrated circuit

A buffer management apparatus that sequentially receives L (L&#x3e;1) types of data and transmits the L types of data to an external device, including: a reception unit that receives data; M (M&#x3c;L) data storage units, each including a buffer area; an interval storage unit that, for each type of data, stores reception interval information; M timing units, that each time an elapsed time from a last storing of data in a corresponding data storage unit, and a control unit that, if all of the data storage units have been allocated, in particular, to different types of data, according to a judgment result based on the elapsed times and the reception interval information, either stores the received data in at least one of the data storage units in place of previously stored data, or transmits the received data to the external device.

Growing community of inventors

Nara, Japan

Daisuke Iwahashi