Panasonic Corporation

Daisuke Imoto

Takashi Yamada

Tetsuji Mochida

Koji Asai

Nobuyuki Ichiguchi

Takehisa Hirano

Katsuhiro Nakai

Kouji Mukai

Wataru Ohkoshi

Tomoaki Tezuka

Kohei Okada

A memory controller () according to this invention includes: a command generation unit () which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit () which issues, to a memory (0), the access commands generated by the command generation unit (). The command generation unit () includes a group determination unit () which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit () generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.

Memory controller, memory system, semiconductor integrated circuit, and memory control method

The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Memory control device, memory device, and memory control method

A memory device according to this invention includes: N internal memory read buses and N internal memory write buses each including a plurality of internal slots; N memory modules; an output data bus and an input data bus each including a plurality of external slots; a read data processing unit which (i) selects, from pieces of data read from the N memory modules via the N internal memory read buses, pieces of data read via two or more internal slots, and (ii) provides the selected pieces of data to external slots of the output data bus; and a write data processing unit which provides each of pieces of data provided via the external slots included in the input data bus, to one of the internal slots included in the N internal memory write buses, so as to write the pieces of data to the N memory modules.

Memory device and memory device control method

In a listening comprehension test using individual examination execution devices, according to the present invention, it is possible to avoid a dishonest act such as peeping at another examinee's answers. An individual examination execution device () reads examination question data and individual information from an examination question storage means () storing the examination questions and an individual information storage means () storing the individual information, respectively. Further, the individual examination device selectively generates actual questions according to the individual information read by an actual question generation means (), and reproduces the actual questions by a reproduction means (), thereby preventing dishonest acts of respective examinees.

Individual examination execution device

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Osaka, Japan

Daisuke Imoto