Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Daisuke Baba

Kyosuke Osuka

Takaaki Yamasaki

Tomoaki Tsutsumi

Kyoko Ueda

An imaging apparatus includes: an image sensor generating original image data; an image processor performing image processing to generate image data; a storage storing a plurality of first parameter sets and at least one second parameter set; and a user interface receiving a user operation combining a first parameter set with a second parameter set. Each of the plurality of first parameter sets defines the effect in the image processing. Each of the at least one second parameter set defines a correspondence before and after color information in an image is converted. Based on the user operation, the image processor: adjusts an image indicated by the original image data, using the first parameter set included in the combination designated by the user operation; and converts color information included in the image adjusted by the first parameter set, using the second parameter set included in the designated combination.

Imaging apparatus

Based on an input index sequence () composed of four indices (each having a bit width of 8 bits), a shift-copier generates an index sequence () by shifting each index leftward by 1 bit and making two copies of each index, and outputs the generated index sequence (). An adder generates a shuffle pattern () by adding 1, 0, 1, 0, 1, 0, 1 and 0 to the indices in the index sequence () from left to right, and outputs the generated shuffle pattern ().

Shuffle pattern generating circuit, processor, shuffle pattern generating method, and instruction sequence

According to the conventional loop parallelization method, when a loop in which a value of a loop-carried dependency variable can be calculated in all of the iterations without sequentially executing the loop from the start, it is determined that DOALL parallelization is not applicable due to the loop-carried dependency variable. Accordingly, the loop is sequentially executed or parallelized by using DOACROSS parallelization that executes a loop including a loop-carried dependency variable. That is, there is a problem that an expression including a loop-carried dependency cannot be parallelized and efficiently processed with use of a multi-processor. By generating initial value calculating codes, the loop-carried dependency in a source code prior to parallelization can be solved, and by dividing a loop included in the source code into subloops that can be executed in parallel, the multi-processor can efficiently process the source code.

Compiler device, compiler program, and loop parallelization method

A decoder reads an instruction for information specifying a bit sequence storage area, information indicating a first bit range, and information indicating a second bit range that is contiguous with the first bit range, then outputs a decoded signal in response to the information so read, and a bit manipulation circuit generates and outputs an output sequence based on a bit sequence stored in the bit sequence storage area by inserting uniform predetermined values between a first bit range and a second bit range in accordance with the decoded signal output from the decoder.

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Osaka, Japan

Daisuke Baba