Sharp Kabushiki Kaisha Corporation

Daisuke Azuma

Souichi Miyata

Koji Komatsu

Shinichi Yoshida

Satoshi Matsumoto

Futoshi Miyamae

Tsuyoshi Muramatsu

Yoshiji Ohta

Toshiya Okamoto

Manabu Onozaki

Shinichi Tanaka

An interface device includes a data transmitter provided with a multiplexer for dividing k.times.n bits of data (k is an integer satisfying k.gtoreq.2) applied from a transmitting side data terminal equipment into k groups for time sequential output, and a data receiver provided with a data latch circuit for taking the first k-1 data groups transmitted from the data transmitter and a data latch circuit for taking the outputs from the k-1 data latch circuits and the last transmitted data group. In a period corresponding to one transmission, two data groups are supplied in time sequence from the data transmitter to the data receiver. There may be provided k data latch circuits so that the inputs of data latch circuit are all passed through the data latch circuits.

Interface apparatus for transferring k*n-bit data packets via

So-called template matching processing is function-distributed into a pre-detecting portion and a template matching portion, processing in the respective portions being achieved by a hardware circuit. In the pre-detecting portion, the relationship between data which simultaneously exist in the determined comparing sections on data transmission paths, and matching processing is performed in advance with respect to data to be matched. The template matching portion includes an addressing type general-purpose memory and performs main processing of template matching based on the result of the comparison and determination in the pre-detecting portion.

Data processor for detecting identical data coexisting in a plurality of

An SRAM is provided wherein each memory cell has first and second storage nodes to be maintained at complementary potentials corresponding to storage data and first and second inverters provided in anti-parallel between the first storage node and the second storage node. Also, a DRAM is provided wherein each memory cell has a single storage node to be maintained at a potential corresponding to storage data and a capacitor provided between the storage node and a low potential source. In each of predetermined memory cells in which storage data is to be initialized, an MOS transistor, which is controlled to turn on for a fixed time period at the time of power supply, is connected between a potential source capable of supplying a potential corresponding to the initialization data and at least one of the first and the second storage nodes (in the case of the SRAM) or between the potential source and the single storage nodes (in the case of the DRAM). In the case of the SRAM, the first or the second inverter in each of the predetermined memory cells is replaced by a two-input NAND gate or a two-input NOR gate for which the output potential at the time of the power supply is controlled to correspond to the initialization data irrespective of the potential at the first (or the second) storage node.

Semiconductor memory device capable of initializing storage data

An interface system for controlling data transmission from a first information processing unit to a second information processing unit includes a handshaking type data transmission path. The handshaking type data transmission path includes a first interface circuit and a second interface circuit. A transmission signal output from the first information processing unit passes the first interface circuit, is then waveform-shaped by the second interface circuit and applied to the second information processing unit. A transmission acknowledging signal output from the second information processing unit passes the first interface circuit and is applied to the first information processing unit. Thus, the timing skews of the signals in the data transmission paths between the first and second information processing units can autonomously be adjusted, thereby preventing further transmission of a transmission signal.

Adaptive interface that automatically adjusts for timing skews caused by

A data flow type information processor includes a program storing portion, a paired data detecting portion, an operation processing portion, an internal data buffer, and an external data memory. A data packet processed in the program storing portion, the paired data detecting portion and the operation processing portion is transferred to the internal data buffer. On the other hand, a data packet outputted from the external data memory is transferred to another information processor through a merge portion, a branch portion, another merge portion and another branch portion. Thus, internal processing through the internal data buffer and processing from the external data memory to the exterior are not merged.

Data flow type information processors where data packets pass through

Data is transferred on respective data transfer paths in an asynchronous manner. Data detecting sections are provided at predetermined positions along the respective data transfer paths. A data detecting devices to detect presence of the data in the respective data detecting sections. A coexistence detecting device is used responsive to the data detecting device to detect simultaneous existence of data in the data detecting sections of a predetermined combination. Data being held in a data holding device is referred to in the corresponding data detecting sections in response to the result of detection by the coexistence detecting device, whereby a plurality of pieces of data are simultaneously referred to among the data being transferred along the data transfer paths in an asynchronous manner.

Data processing apparatus for processing asynchronous data in an

Data processor for detecting identical data simultaneously coexisting in

A first-in first-out type memory is used as a buffer for data transfer between asynchronous systems. This buffer memory has a minimum delay elastic buffer function in which the number of data storage stages is changed according to the data transfer situation in an output portion of the memory. The data storage memory includes a folded type data transmission path with a going path and a returning path respectively provided with data storage devices of the same number, bypassing paths for coupling corresponding data storage devices in the going path and the returning path, and a valid data detector provided corresponding to each of the bypassing paths for detecting the presence or absence of valid data in a data storage device closer to an input/output portion than a corresponding bypassing path and making the bypassing path enabled or disabled according to the result of the detection.

FIFO buffer with folded data transmission path permitting selective

A data transmission apparatus comprises a plurality of first data transmission paths, a second data transmission path, and an arbitration control portion. Priorities are respectively given to the plurality of first data transmission paths. A plurality of first data transmission paths receive a plurality of data applied through a plurality of input-side data transmission paths. When the plurality of data stay in the input-side data transmission paths, the arbitration control portion performs control such that data is transmitted from a first data transmission path having the higher priority to the second data transmission path.

Data transmission apparatus

Two input-side data transmission paths are provided in parallel with each other, and a competition detecting part detects the time difference between times of arrival of transmission signals supplied to the respective data transmission paths for stopping the data arriving with a delay on the data transmission path therefor if the time difference is within a constant range. Thereby, the time difference is rendered to be outside of the constant range. A word number counting part counts the word numbers of the data transmitted to the data transmission paths, and an arbitration control part supplies transmission authorizing signals to the respective input-side data transmission paths for transmitting the data of the counted word numbers to an output-side data transmission path. The two input-side data transmission paths are provided with buffer mechanisms for changing the amounts of data delay in response to the degree of data occupancy.

Data transmission unit

A semiconductor IC element is three-dimensionally structured with a first active layer formed on a single crystalline silicon substrate and a second active layer formed by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates it from the first layer. Each active layer is comprised of single crystalline areas where transistors may be formed and separation areas which insulate them. PMOS, NMOS or CMOS field effective transistors are formed on these active element areas. A test circuit for testing the originally intended functions of the element as well as its redundant circuits may be formed on these layers. Throughholes are provided to connect the vertically separated active layers.

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Nara, Japan

Daisuke Azuma