Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Infineon Technologies Ag

Other

Daisaburo Takashima

Ryu Ogiwara

Yukihito Oowaki

Shinichiro Shiratake

Hidehiro Shiga

Takahiko Iizuka

Tadashi Miyakawa

Kosuke Hatsuda

Kenji Tsuchida

Katsuhiko Hoya

Yasushi Nagadomi

Sumio Tanaka

Yoshiaki Takeuchi

Daisuke Hashimoto

Kohei Oikawa

Daisuke Kato

Yoshiaki Asao

Tsuneo Inaba

Ryo Fukuda

Mizuki Ono

Thomas Roehr

Shigeyoshi Watanabe

Masahiro Kamoshida

Michael Jacob

Yukihiro Nomura

Mitsuhiro Noguchi

Akira Nishiyama

Tohru Ozaki

Yoshiki Kamata

Misako Morota

Sumiko Domae

Sumiko Doumae

Masako Ohta

Shinichi Kanno

Hiroaki Nakano

Takeshi Hioka

Norbert Rehm

Takaya Suda

Rieko Funatsuki

Shuso Fujii

Nobert Rehm

Tomoki Chiba

Takashi Ohsawa

Takuya Futatsuyama

Takeshi Hamamoto

Hiroshi Sukegawa

Takeshi Watanabe

Takashi Kawakubo

Kazuhide Abe

Masaki Momodomi

Takehiro Hasegawa

Kazunori Ohuchi

Ryousuke Takizawa

Joerg W Wohlfahrt

Masahiro Takahashi

Shigeru Kawanaka

A memory device includes a memory cell and a first select transistor. The memory cell includes a variable resistance memory region, a first semiconductor layer being in contact with the variable resistance memory region, a first insulating layer being in contact with the first semiconductor layer, and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes a second semiconductor layer, a second insulating layer being in contact with the second semiconductor layer, and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.

Memory device with memory strings using variable resistance memory regions

According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.

Semiconductor memory device

A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

Semiconductor storage device

In a nonvolatile semiconductor memory device, in a cell block, a local bit line is connected to a bit line via a select transistor. The local bit line extends in a third direction. A local source line is connected to a source line and extends in the third direction. A plurality of memory cells are connected in parallel between the local source line and the local bit line. Each of the memory cells includes a cell transistor and a resistance change element. The cell transistor has a gate connected to a corresponding one of the word lines and one end connected to one of the local bit line or the local source line. The resistance change element is connected between the other end of the cell transistor and the other one of the local bit line or the local source line.

Nonvolatile semiconductor memory device with a plurality of memory cells arranged in a three-dimensional direction

A variable resistance non-volatile memory includes a semiconductor substrate, a first electrode line extending in a first direction away from the semiconductor substrate, a second electrode line extending in the first direction parallel to the first electrode line, an insulating film between the first and second electrode lines, a variable resistance film formed on the first electrode line, a low electrical resistance layer formed on the variable resistance film and having a lower electrical resistance than the variable resistance film, a semiconductor film in contact with the low electrical resistance layer and the insulating film, and formed on opposite surfaces of the second electrode line, a gate insulator film extending in the first direction and in contact with the semiconductor film, and a voltage application electrode that extends in a second direction that crosses the first direction, and is in contact with the gate insulator film.

Variable resistance non-volatile memory with a gate insulator film at a same height as a voltage application electrode

According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.

Three dimensional stacked semiconductor memory

A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Memory device and method of manufacturing memory device

A memory device includes a memory cell array including a select transistor and a plurality of memory cells connected in series, each memory cell including a cell transistor and a variable resistance layer connected in parallel. During a write operation, a voltage setting circuit is controlled to apply a first voltage to a selected word line and a second voltage to non-selected word lines. The time period for applying the first voltage to the selected word line starts later than the time period for applying the second voltage to the non-selected word lines and ends earlier than the time period for applying the second voltage to the non-selected word lines.

Memory device

A nonvolatile memory includes a first memory cell and a second memory cell above the first memory cell. The first memory cell includes a variable resistance layer extending in a first direction, a semiconductor layer extending in the first direction and in contact with the variable resistance layer, an insulator layer extending in the first direction and in contact with the semiconductor layer, and a first voltage applying electrode extending in a second direction and in contact with the insulator layer. The second memory cell includes a second voltage applying electrode in contact with the insulator layer. When a write operation is performed on the first memory cell, a first voltage is applied to the second voltage applying electrode, and when a write operation is performed on the second memory cell, a second voltage, lower than the first voltage, is applied to the first voltage applying electrode.

Variable resistance nonvolatile memory

According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell.

According to one embodiment, there is provided a nonvolatile semiconductor memory device including a cell array. The cell array includes an array of a plurality of string blocks. Among the plurality of local string blocks, one local string block includes a block selection transistor and remaining local string blocks do not include a block selection transistor. A gate terminal of the block selection transistor of the one local string block is connected to a block selection line. Signals of two word lines connected to two adjacent string blocks in the bit line direction are common signals. Signals of two block selection lines connected to the two adjacent string blocks are independent of each other.

Nonvolatile semiconductor memory device

According to one embodiment, a memory device includes: a plurality of memory cells stacked in a first direction orthogonal to a substrate and each including a memory element having at least three resistance states and a selector coupled in parallel to the memory element; a bit line electrically coupled to the memory cells and extending in a second direction intersecting the first direction; and a sense amplifier configured to compare a voltage of the bit line with a plurality of reference voltages and sense data stored in the memory cells.

Memory device having sense amplifier including plural sense circuits for sensing a voltage of a bit line in a read operation

According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.

Growing community of inventors

Yokohama, Japan

Daisaburo Takashima