Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Daiki Watanabe

Hironori Uchikawa

Kosuke Morinaga

Hiroshi Yao

Daisuke Fujiwara

Ryo Yamaki

Naoaki Kokubun

Naoko Kifune

Hiroshi Sukegawa

Tokumasa Hara

Osamu Torii

Naomi Takeda

Kenji Sakurada

Yuta Kumano

Masahiro Kiyooka

Yoshiki Notani

Noboru Shibata

Takeshi Ishihara

Takahiro Shimizu

Haruka Obata

Takahiro Kubota

Manabu Sato

Kenji Shirakawa

Takahiro Fujiki

Yuchieh Lin

Yuma Yoshinaga

A method for executing query processing includes, in response to a query from a host, generating a task graph indicating a plurality of task sequences, each of the task sequences capable f performing query processing corresponding to the query. The sequences includes a first sequence that outputs data in a first compression state to a one of output targets, and a second sequence of tasks that outputs the data in a second compression state different from the first compression state to the one of the output targets. The method further includes determining a processing cost for each of the task sequences, selecting one of the task sequences in accordance with the determined processing cost, and performing the query processing corresponding to the query in accordance with the selected task sequence.

Method and database system for optimizing query processing execution scheme

According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Soft decoding method using LLR conversion table

A memory system includes a non-volatile memory configured to store an N-dimensional error correction code and a memory controller. The memory controller is configured to calculate an asoft-input value for an acomponent code based on correction information of the acomponent code (1&#x2264;a&#x2264;ni) of an idimension (1&#x2264;i&#x2264;N), areliability information, and a syndrome value of the acomponent code, to calculate a decoded word of the acomponent code, the acorrection information, and the areliability information by inputting the asoft-input value and executing a decoding process of the acomponent code, to store the acorrection information and bcorrection information indicating a corrected position of a bcomponent code (1&#x2264;b&#x2264;nj) of a jdimension (j&#x2260;i, 1&#x2264;j&#x2264;N) in a correction information memory, to store the areliability information in a reliability information memory, and to output an output decoded word calculated from the read information and the reliability information of each component code.

Memory system

Memory system and control method

A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller converts a received value read from the nonvolatile memory into first likelihood information by using a first conversion table, executes decoding on the first likelihood information and outputting a posterior value, outputs an estimated value of the received value obtained on the basis of the posterior value in a case where the decoding is successful. The memory controller generates a second conversion table on the basis of the posterior value in a case where the decoding fails. The memory controller converts the received value into second likelihood information by using the second conversion table in a case where the second conversion table has been generated, and executes decoding on the second likelihood information and outputs a posterior value.

Memory system and method for controlling nonvolatile memory

According to one embodiment, a memory system includes a nonvolatile memory, an encoding part configured to generate a plurality of component codes including a first component code and a second component code different from the first component code, by using, as an information symbol, at least one symbol of a plurality of symbols included in user data to be written into the nonvolatile memory, and a memory interface configured to write the plurality of component codes into the nonvolatile memory. The encoding part includes a plurality of encoders each configured to generate a parity corresponding to each of the plurality of component codes, and a first distributor configured to divide a first symbol string of the user data into a plurality of chunks, each of which has a first symbol length smaller than that of the first symbol string, and to input each of the plurality of chunks generated by the division, into any one of at least different two of the plurality of encoders. The memory interface is configured to write the first symbol string and parities corresponding to the first symbol string into the nonvolatile memory.

Memory system including an error correction function

A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller generates an error correction code including a first and second symbol groups. The first symbol group is a set of symbols shared between a first component code and a third component code and/or a fourth component code. The second symbol group is a set of symbols shared between a second component code and the third component code and/or the fourth component code. The first and third component codes have a lower correction capability than the second and fourth component codes, respectively. The ratio of symbols protected by the third component code is smaller in the second symbol group than in the first symbol group. The ratio of symbols protected by the fourth component code is larger in the second symbol group than in the first symbol group.

Memory system and method for controlling non-volatile memory

A memory system in an embodiment includes a nonvolatile memory and a memory controller. The memory stores a multi-dimensional error correction code including at least one symbol that is capable of being protected by at least a first and a second component code. The controller reads the error correction code from the memory, executes hard decision decoding of the first component code with respect to the read error correction code and outputs a first decoding result and index information for calculating likelihood of the first decoding result, executes, when the hard decision decoding fails, soft decision decoding of the second component code by using the first decoding result and the index information and outputs a decoding result as a hard bit, and, executes, when the soft decision decoding fails, the hard decision decoding with respect to the result of the soft decision decoding output.

Memory system and method of controlling nonvolatile memory

According to one embodiment, a memory system includes a first decoder that decodes read information read from a nonvolatile memory that records therein a multidimensional error-correcting code to output hard decision decoding information of each symbol; a second decoder that performs soft decision decoding in units of component codes for the read information using a soft-input value to output soft decision decoding information of each symbol; a soft-decision-decoding information memory that retains the soft decision decoding information of each symbol; and a soft-input-value specifying unit that obtains the soft-input value of each symbol using the read information and the hard decision decoding information or the soft decision decoding information, and the soft-input-value specifying unit obtains an initial value of the soft-input value using the read information and the hard decision decoding information, and outputs an output decode word obtained as a result of the soft decision decoding when the output decode word is determined to be correct.

Memory system and method of controlling non-volatile memory

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller calculates a reliability metric on the basis of at least a soft-decision input value calculated on the basis of read information that is read from the nonvolatile memory, and a decoded word, stores reference information that is a history of a plurality of reliability metrics or statistical information obtained from the history, calculates reliability from the reliability metric by using correspondence information, calculates decoding information on the basis of the decoded word and the reliability, and updates the correspondence information on the basis of the reference information.

Memory system and decoding method

According to one embodiment, a memory system includes an intermediate value memory that holds decoded words of first and second component codes and reliability information and calculates a soft-input value of the first component code based on at least a decoded word concerning the second component code and reliability information and read information, decodes the soft-input value of the first component code, thereby calculating a decoded word of the first component code and reliability information, updates the intermediate value memory with the calculated decoded word and reliability information, calculates a soft-input value of the second component code based on at least the decoded word of the first component code and the reliability information and read information, decodes the soft-input value of the second component code, thereby calculating a decoded word of the second component code and reliability information, and updates the intermediate value memory with the calculated decoded word and reliability information.

A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets r(ris a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the r) symbols of the rsymbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values.

Memory controller, memory system, and control method

According to an embodiment, a memory system includes: a test pattern decoding unit that detects an intermediate decoding word from a plurality of test patterns; a Euclid distance calculating unit that calculates a Euclid distance between the intermediate decoding word and a received word; and a maximum likelihood decoding word selecting unit that maintains a maximum likelihood decoding word candidate. In a case where a Euclid distance of the intermediate decoding word is shorter than a Euclid distance of the maximum likelihood decoding word candidate, the maximum likelihood decoding word selecting unit updates the maximum likelihood decoding word candidate by using the intermediate decoding word and the test pattern decoding unit does not execute decoding of a test pattern having no possibility that the Euclid distance of the intermediate decoding word becomes shorter than the Euclid distance of the maximum likelihood decoding word candidate.

According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.

Decoding device and decoding method

According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimension is different from that of the first component code; determine whether the first rewriting process is erroneous correction based on a result of the second decoding process; and when it is determined that the first rewriting process is erroneous correction, perform a counter process which is undoing the first rewriting process based on the recorded first recurrence information.

Growing community of inventors

Yokohama, Japan

Daiki Watanabe