Renesas Electronics Corporation

Japan Science and Technology Agency

Daiki Kitagata

Shinji Tanaka

Satoshi Sugahara

Toshiaki Sano

Shuichiro Yamamoto

Kouji Satou

A plurality of SRAM macros each including a memory cell array, an input/output circuit, a word line driver, and a control circuit are mounted on a semiconductor chip. Each of the SRAM macros includes a determination block disposed in the control circuit and configured to generate a mode signal for determining a read assist amount and a write assist amount based on a power supply voltage of the SRAM macro, and an assist circuit that performs a read assist operation and a write assist operation based on the mode signal generated by the determination block.

Semiconductor chip including SRAM macros

A semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data holding circuit, a second data holding circuit, a third data holding circuit, a fourth data holding circuit, and an input line. A characteristic value of the memory cell is changeable by controlling the switch connected to the first data line among the plurality of switches based on a value held by the third data holding circuit and by controlling the switch connected to the second data line among the plurality of switches based on a value held by the fourth data holding circuit.

Semiconductor device

An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.

Growing community of inventors

Tokyo, Japan

Daiki Kitagata