Denso Corporation

Daihan Wang

Takeshi Kondo

Hirofumi Yamamoto

Shinichirou Taguchi

Tomoyoshi Funazaki

Yukoh Matsumoto

Takatoshi Nomura

A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.

Multi-core processor using former-stage pipeline portions and latter-stage pipeline portions assigned based on decode results in former-stage pipeline portions

Growing community of inventors

Okazaki, Japan

Daihan Wang