Micron Technology Incorporated

Daigo Toyama

Yuan He

Chikara Kondo

Takamasa Suzuki

Katsuhiro Kitagawa

Yoshihito Morishita

Takehiro Hasegawa

Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

Apparatuses, systems, and methods for system on chip replacement mode

Apparatuses, systems, and methods for faster memory access regions. A memory array may have a first bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

Apparatuses including memory regions having different access speeds and methods for using the same

A cold data detector circuit includes a bubble break register that is configured to detect cold data in a memory system including main memory and secondary memory. The bubble break register selectively shifts received segment addresses to fill empty slots without having to wait until the empty slots are shifted out an end slot, and may provide an indication of cold data in response to every slot of the register being filled with a different respective segment address.

Cold data detector in memory system

Apparatuses, methods, and computing systems relating to three-dimensional fuse architectures are disclosed. An apparatus includes a semiconductor substrate, a fuse array on or in the semiconductor substrate, and fuse circuitry on or in the semiconductor substrate. The fuse array includes fuse cells. The fuse circuitry is configured to access the fuse cells. The fuse circuitry is offset from the fuse array such that the fuse circuitry is disposed between the semiconductor substrate and the fuse array, or the fuse array is disposed between the semiconductor substrate and the fuse circuitry.

Three-dimensional fuse architectures and related systems, methods, and apparatuses

An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory army access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.

Apparatuses and methods to perform low latency access of a memory

Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.

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Fujisawa, Japan

Daigo Toyama