Sony Computer Entertainment Inc.

Elpida Memory, Inc.

Sony Corporation

Micron Technology Incorporated

Ps4 Luxco S.a.r.l.

Mitsumi Electric Company Ltd.

Mitsubishi Denki Kabushiki Kaisha

Murata Manufacturing Co., Ltd.

Sony Interactive Entertainment Inc.

Dai Sasaki

Mitsuaki Katagiri

Satoshi Isa

Shiho Moriai

Hisashi Tanie

Hiroshi Moriya

Yu Hasegawa

Hiromasa Takeda

Satoshi Itaya

Ken Iwakura

Toshiyuki Kurosaki

Masahiko Hayakawa

Taichi Sasaki

Kazutaka Koshiishi

Jun Kayamori

Masao Okubo

Muneki Shimada

Toru Akazawa

Masafumi Kusakawa

Koji Hayashi

Terutomo Kajiwara

Masuo Kato

Tohru Terasaki

Sumio Morioka

Shuji Wakafuji

Mitsuaki Katagirl

Masami Tsurumi

Taisuke Koga

Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

Apparatuses comprising semiconductor dies in face-to-face arrangements

A semiconductor device includes a package substrate, an IF chip, and a core chip. The package substrate has: first electrodes aligned and disposed on a first rear surface; second electrodes aligned and disposed in the first direction (Y direction) on a first front surface; and wiring that electrically connects the first electrodes and the second electrodes. The IF chip has third electrodes bonded to the second electrodes. The core chip is connected to the IF chip. In the first direction, the length of the IF chip is more than that of the core chip but equal to or less than that of the package substrate. One of the first electrodes is disposed further toward the outside than a core chip end portion in the first direction. At least one of the second electrodes is disposed further toward the outside than the core chip end portion in the first direction.

Semiconductor device

In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

Semiconductor device stack with bonding layer and wire retaining member

Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array.

A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted.

Semiconductor device and stacked semiconductor device

An AC adapter including an electronic device, a first circuit board on which the electronic device is mounted, a second circuit board separated from the first circuit board, a connector mounted on the second circuit board and electrically connected to the second circuit board, first and second metal wirings that electrically connect the first and the second circuit boards, and an insulation case installing the first circuit board, the electronic device, the second circuit board, and the connector therein and including a projecting part interposed between the first and second metal wirings.

AC adapter

A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.

Semiconductor device and method of bonding wires between semiconductor chip and wiring substrate

In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

Semiconductor device including semiconductor chips with different thickness

A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substratesare on the upper surface of semiconductor chip. First additional wiring layer for power sourceand first additional wiring layer for groundformed on respective additional substratesform prescribed conductive areas on semiconductor chip. First power source wiringCor first ground wiringCare interconnected through additional wiring layersand. Second power source wiringCand second ground wiringC, which is extended in the same direction as with DQ system signal wiringC, forms a feedback current path. Second power source wiringCand second ground wiringCare disposed adjacent to DQ system signal wiringC.

Semiconductor device with additional power supply paths

A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length Lfor connecting the first semiconductor chip to the substrate, a second bonding wire having a length L(where L&#x3e;L) for connecting the second semiconductor chip to the substrate, a first resin seal having a dielectric constant &#x2208;for sealing the first bonding wire, and a second resin seal having a dielectric constant &#x2208;(where &#x2208;&#x3c;&#x2208;) for sealing the second bonding wire. The relationship between the lengths Land Land the dielectric constants &#x2208;and &#x2208;is defined by an equation of &#x2208;=&#x2208;(L/L).

Growing community of inventors

Tokyo, Japan

Dai Sasaki