Samsung Electronics Co., Ltd.

Daewon Ha

Sungmin Kim

Sungil Park

Munhyeon Kim

Jung Hyuk Lee

Soonmoon Jung

Mingyu Kim

Jae Hyun Park

HyoJin Kim

Keun Hwi Cho

Sung-Dae Suk

Kwang-woo Lee

Doyoung Choi

Dongwon Kim

Jaehyun Park

Kyunghwan Lee

Byounghak Hong

Harsono S Simka

Uihui Kwon

Kwangjin Lee

Kyungho Kim

Jaehoo Park

Keunhwi Cho

Seungseok Ha

Dongho Cha

Daehwan Kang

Rebecca Park

Ming He

Young-Joo Jeon

Byoung Hak Hong

Gitae Jeong

Mehdi Saremi

Cheoljin Yun

Yongseok Kim

Hyo-Jin Kim

Hyuncheol Kim

Jason Martineau

Kang-ill Seo

Seunghyun Song

Myunggil Kang

Kang-Ill Seo

Hwichan Jun

Inchan Hwang

Song Yi Kim

Kyu-Rie Sim

Seungchan Yun

Jeonghyuk Yim

Yonghee Park

Gunho Jo

Youngmoon Choi

Minjun Lee

Joohyung You

JaeHoo Park

Jihyung Yu

JaeHyun Park

Chihak Ahn

Kyuman Hwang

Woonggi Kim

A three-dimensional semiconductor device comprises a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a first active contact electrically connected to the lower source/drain pattern, an upper separation structure between the first active contact and the upper source/drain pattern, a second active contact electrically connected to the upper source/drain pattern, and a lower separation structure between the second active contact and the lower source/drain pattern.

Three-dimensional semiconductor device and method of fabricating the same

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Nanosheet transistor devices and related fabrication methods

A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.

Memory device

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods

A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.

Semiconductor device

A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

A method of manufacturing a semiconductor device includes forming a first sacrificial and first active layer on a substrate; forming a first mask pattern on a portion of the substrate; etching the first sacrificial and first active layer partially using the first mask pattern to expose a portion of a top surface of the substrate; forming a semiconductor layer on the exposed top surface of the substrate; forming sacrificial layers and active layers on the first active and semiconductor layer, the active layers including an uppermost second active layer; forming a second mask pattern on a portion of the second active layer; forming a trench using the second mask pattern, the trench defining a first and second active pattern; and removing the sacrificial layers to form a first and second channel patterns on the first and second active patterns, respectively, wherein the first active pattern includes the semiconductor layer.

Methods of manufacturing a semiconductor device using a mask

Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity.

Selective single diffusion/electrical barrier

A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

An integrated circuit device according to the inventive concept includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a stopper layer that is above and spaced apart from the fin-type active area; a gate electrode extending in a second horizontal direction orthogonal to the first horizontal direction, on the fin-type active area, and in a space between the fin-type active area and the stopper layer; and a gate capping layer on upper surfaces of the gate electrode and the stopper layer.

Integrated circuit devices having uniformly formed structure

A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

Semiconductor devices with stacked transistor structures

Growing community of inventors

Seoul, South Korea

Daewon Ha