Yangtze Memory Technologies Co., Ltd.

Daesik Song

Zhichao Du

Yu Wang

Huangpeng Zhang

Qiang Tang

Xiaojiang Guo

Zhuqin Duan

Ke Jiang

Hang Song

Cong Luo

Lin Y Yang

Yan Wang

Xiaodong Mei

ZhiChao Du

Lin Yang

Debo Wei

Jae Hyeong Kim

Danyang Li

James Kim

According to one aspect of the present disclosure, a memory is provided. The memory may include a row hammer control circuit including a plurality of counters. Each of the plurality of counters may count a number of accesses of one memory row. Each of the plurality of counters may be configured to generate a first count value. The memory may include an adjustment circuit connected with the plurality of counters. The adjustment circuit may reset each of the plurality of counters when each of a plurality of first count values reaches a target threshold. The adjustment circuit may adjust each of the first count values by a same offset value to generate a plurality of second count values. The row hammer control circuit may determine a target memory row according to the plurality of second count values.

Memory and operation method thereof and memory system

A memory device includes a memory array having memory cells, a page buffer coupled to the memory array through bit lines and including a latch, and a control logic coupled to the page buffer. The control logic is configured to perform a first read operation on the memory cells, and perform a second read operation on the memory cells by dividing the memory cells into a plurality of groups of memory cells, and performing a second read operation on the plurality of groups of memory cells based on a first set of develop times. Each of the first set of develop times is different. The control logic is also configured to perform a third read operation on the memory cells by performing a third read operation on the plurality of groups of memory cells based on a second set of develop times. Each of the second set of develop times is different. The control logic is further configured to determine a read develop time based on the third read operation.

System and method of performing a read operation

In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver. The circuit can further include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a replica of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the replica, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a middle point between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator.

Multi-mode compatible ZQ calibration circuit in memory device

A page buffer includes a first charge/discharge circuit and a second charge/discharge circuit coupled to a bit line. The first charge/discharge circuit is configured to store first bit line forcing information and apply a first bit line forcing voltage to the bit line based on the first bit line forcing information. The second charge/discharge circuit coupled to the bit line and configured to store a second bit line forcing information, and apply a second bit line forcing voltage, different from the first bit line forcing voltage, to the bit line based on the second bit line forcing information. The first bit line forcing voltage and the second bit line forcing voltage are both higher than a programming bit line voltage and lower than a programming-inhabit bit line voltage.

Page buffer, memory device, and method for programming thereof

In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.

Memory device and program operation thereof

A memory includes a peripheral circuit and a memory array. The memory array includes word lines. The peripheral circuit includes a driver, a repeater, and a discharge circuit. An output terminal of the driver is coupled with a controlled terminal of the repeater. An output terminal of the repeater is coupled with a controlled terminal of the discharge circuit. The discharge circuit is coupled with a word line in the memory array. The driver is configured to output a first control signal to the repeater. The repeater is configured to output a second control signal to the discharge circuit according to the first control signal.

Memory, drive method, memory system, and electronic device

The present disclosure provides a three-dimensional NAND memory device, comprising memory cells coupled to a plurality of word lines and configured to store data, a row decoder configured to decode an address of a word line from the plurality of word lines, and a controller coupled to the array of memory cells. The controller includes a first multiplexer configured to receive a first plurality of trim selections, while each of the first plurality of trim selections is associated with a first trim parameter and each of the first plurality of trim selections corresponds to each of the plurality of word lines, respectively. The controller also includes a second multiplexer configured to receive a first plurality of trim settings, while each of the first plurality of trim settings corresponds to a value associated with the first trim parameter.

Control method and system in 3D NAND systems

The present disclosure provides a memory device, comprising a memory array having memory cells, a page buffer coupled to the memory array through bit lines. The page buffer comprises a latch, and a control logic coupled to the page buffer and configured to: perform a first read operation on the memory cells; select, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state, based on the first read operation; perform a second read operation on the first plurality of memory cells; select, from the first plurality of memory cells, a third plurality of memory cells based on the second read operation; perform a third read operation on the third plurality of memory cells; and determine a read develop time based on the third read operation.

In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.

A method for a memory device having memory dies includes performing high power portions of array operations in the memory dies, ending the high power portions in the memory dies, generating a register signal after ending the high power portions, and in response to obtaining the register signal, commencing one or more input/output (I/O) operations in the memory dies.

Power management mechanism and memory device having the same

A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Memory system and peak power management for memory dies of the memory system

Peak power management for multi-die operations

A double data rate circuit includes a clock generator, a clock divider and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the clock generator, and used to generate four multiphase clock signals using only single-edge transitions of the pair of complementary clock signals. The four multiphase clock signals are successively out-of-phase by 90&#xb0;. The multiplexer is coupled to the clock divider, and used to multiplex multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits upon a first edge transition of and a second edge transition of two of the four multiphase clock signals, respectively, and outputting each selected data bit as the output data stream.

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Hubei, China

Daesik Song