Micron Technology Incorporated

Daesik Song

Qiang Tang

Eric N Lee

Ali Feiz Zarrin Ghalam

Hoon Choi

Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal

Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal

Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

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Sunnyvale, CA, United States of America

Daesik Song