Samsung Electronics Co., Ltd.

Daeshik Kim

Gwanhyeob Koh

Yongdon Kim

Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells and divided into a first region and a second region, and a sensing circuit that generates a first read current for determining data stored in memory cells belonging to the first region from among the plurality of memory cells wherein the second region configured to store a value of the first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a memory cell where the data is stored and a value of an initial read current applied to the memory cell.

Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell

Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.

Memory device which generates improved write voltage according to size of memory cell

Disclosed is a memory device including a magnetic storage element. The memory device includes a memory cell array, a voltage generator, and a write driver. The memory cell array includes a first region and a second region. The memory device is configured to store a value of a first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a programmed memory cell. The sensing circuit is configured to generate the first read current based on the value of the first read current and to perform a read operation on the first region based on the first read current.

Memory device which generates improved read current according to size of memory cell

A memory device includes; a memory cell array including a first memory cell region and a second memory cell region, a voltage generator configured to generate a code corresponding to a write voltage, and a write driver configured to store data in the first memory cell region in response to the code. The second memory cell region stores a value defining the write voltage, and the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

Memory device generating optimal write voltage based on size of memory cell and initial write voltage

A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate. A second semiconductor chip comprises a second substrate. A second magnetic tunnel junction is on the second substrate. The second semiconductor chip is positioned on the first semiconductor chip to form a chip stack. A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction.

Semiconductor device

A nonvolatile memory device includes: first memory cells connected to a first source line and a first bit line; second memory cells connected to a second source line and a second bit line; and a sense amplifier circuit connected to the first and second source lines and the first and second bit lines. The sense amplifier circuit includes: a first sense amplifier configured to apply a first read voltage to the first bit line and output a first amount of current of a selected first memory cell; a second sense amplifier configured to apply a second read voltage to the second bit line and output a second amount of current of a selected second memory cell; and a comparator configured to compare the first amount of current with the second amount of current to identify data of the selected first memory cell.

Nonvolatile memory device including reference memory cell with fixed state

A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern disposed on the interlayer dielectric and having a central axis laterally offset from a central axis of the contact plug, a pad extending on the contact plug and along a sidewall of the pillar pattern, the pad being electrically connected to the contact plug, and a data storage portion on the pillar pattern and electrically connected to the pad.

Provided is a data writing method of a magnetic memory device. The method may include flowing first and second currents near left and right sides, respectively, of a selected memory cell to apply an ambient magnetic field to the selected memory cell. Here, directions of the first and second currents may be anti-parallel to each other.

Methods of operating a magnetic memory device

A semiconductor device comprises a device isolation pattern, an active region, a gate pattern, a first source/drain region, and a first barrier region. The device isolation pattern defines an active portion in a semiconductor substrate and the active portion comprises first and second sidewalls extending in a first direction and doped with a first conductive type dopant. The gate pattern extends in a second direction perpendicular to the first direction to cross over the active portion. The first source/drain region and the first barrier region are disposed in the active portion at one side of the gate pattern. The first barrier region is disposed between the first source/drain region and the first sidewall and contacts the first sidewall. The first barrier region is doped with the first conductive type dopant and the first source/drain region is doped with a second conductive type dopant.

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Hwaseong-si, South Korea

Daeshik Kim