Samsung Electronics Co., Ltd.

Lg Semicon Co., Ltd.

Goldstar Electron Co., Ltd.

Daejeong Kim

Dohan Kim

Insu Choi

Namhyung Kim

Deokho Seo

Wonjae Shin

Minsu Kim

Chanik Park

Changmin Lee

Ilguy Jung

Sung Ho Cho

Deog-Kyoon Jeong

Hoyoung Lee

Sungho Wang

Taekyeong Ko

Jaein Song

A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.

Memory system, operating method of the same, and controller of memory device

A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

Memory device, memory module including the memory device, and operating method of memory controller

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

Memory device capable of outputting fail data in parallel bit test and memory system including the memory device

Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator

Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

Memory device skipping refresh operation and operation method thereof

An improved CMOS current source circuit capable of constantly generating a certain reference voltage irrespective of an analog supplying voltage, a substrate temperature, and a temperature variation, which includes a start unit for driving the CMOS current source circuit in accordance with a start signal; a bias current generating unit driven by the start unit for generating a bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation; a current input unit for inputting a bias current; and a current compensation unit for receiving a bias current through the current input unit and for compensating the bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation and for generating a reference current.

CMOS current source circuit

A reference voltage generating circuit of a semiconductor device includes a start-up circuit connected to a reference current generator, a substrate variation sensor and a temperature compensation current- to-voltage converter receiving outputs from the generator and sensor. The start-up circuit is connected to a reset terminal, for generating a driving signal determining an operating point of the reference voltage generating circuit. The reference current generator has a current mirror of a constant current source for receiving the driving signal from the start-up circuit and generating a reference current. The reference current generator includes a voltage divider for determining the reference current. The substrate voltage variation sensor compensates for a variation of the reference current caused by the variation of a substrate voltage. The current-to-voltage converter converts the reference current to a reference voltage; and the temperature compensator connected to the output terminal, compensates for the variation of the reference current due to the variation of temperature.

Reference voltage generating circuit

A .DELTA..SIGMA. digital/analog converter comprising an interpolator for sampling an input digital signal at a desired ratio, a noise-shaping coder for quantizing an output signal from the interpolator into the coded bits and modulating a quantization error generated in the quantization, a differentiator for detecting an intersignal variation from an output signal from the noise-shaping coder, the intersignal variation indicating a difference between previous and present digital signal values, a digital logic unit for generating a desired control signal according to the intersignal variation detected by the differentiator, an internal digital/analog converter for performing charging and discharging operations in response to the desired control signal from the digital logic unit to output an analog signal corresponding to the input digital signal, and a filter for filtering an output signal from the internal digital/analog converter to remove a mixed noise therefrom. According to the present invention, a minimized number of passive devices is used to reduce an error amount resulting from a process deviation, miniaturize a chip and easily enhance the internal bits without expanding the chip size.

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Seoul, South Korea

Daejeong Kim