Samsung Electronics Co., Ltd.

Daehyun Kwon

Hyejung Kwon

Hyeran Kim

Chisung Oh

Jaemin Choi

Jaehyeok Baek

Buyeon Lee

Jang-Woo Ryu

Hangi Jung

Byoungsul Kim

Donghee Kim

Youngsan Kang

Byung Yo Lee

Donggun An

Jin Kwan Park

Chang-hyun Bae

Sanguk Lee

Yejin Jo

Hye-ran Kim

Jang Hoo Kim

Sungoh Huh

Myong-Seob Song

Daewoong Lee

Saetbyeol Kim

Hye-seung Yu

Yoo-chang Sung

A memory module includes a plurality of memory devices. Each of the plurality of memory devices includes a plurality of data input/output pads, a plurality of on-die termination (ODT) circuits each including one or more resistors, a plurality of transceiver circuits each including one or more transmission drivers and one or more reception buffers, and a plurality of equalizer circuits each including one or more inductors. Each of the plurality of equalizer circuits is connected to one of the plurality of data input/output pads, one of the plurality of ODT circuits, and one of the plurality of transceiver circuits. Each of the one or more transmission drivers drives a node of one of the plurality of data input/output pads. Inductances of the one or more inductors have individual values which are based on a driver strength of each of the one or more transmission drivers.

Memory module and electronic system including the same

A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

Multiplexer and serializer including the same

An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

Apparatus, memory device and method for storing parameter codes for asymmetric on-die-termination

An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

Semiconductor memory devices having efficient serializers therein for transferring data

A calibration circuit includes a first, second and third pull-up units each connected to a first power supply node, and first and second pull-down units each connected to a second power supply node. A first code generator is configured to generate a first code by comparing a voltage of a pad at which the first pull-up unit is connected to an external resistor with a reference voltage, and a second code generator is configured to generate a second code by comparing a voltage of a first intermediate node with the reference voltage and output the second code to the first and second pull-down units. A third code generator is configured to generate a third code by comparing a voltage of a second intermediate node between the second pull-down unit and the third pull-up unit with the reference voltage.

Calibration circuit and semiconductor device including the same

An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.

Electronic device, system-on-chip, and operating method thereof

An integrated circuit device, a semiconductor substrate, and a test system including the integrated circuit device are disclosed. The integrated circuit device includes a power terminal configured to receive a source voltage, a power via connected to the power terminal and passing through at least one of a number of layers, a number of inductive vias arranged apart from the power via and passing through at least one of the number of layers, a number of wirings connected to ends of at least some of the number of inductive vias and configured to form a coil wound in toroidal form together with the number of inductive vias, around the power via, and a test terminal configured to output an induced voltage in the coil externally of the integrated circuit device, in response to the supply of the source voltage.

Integrated circuit device, semiconductor substrate, and test system including the integrated circuit device

A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

Data receiving devices, memory devices having the same, and operating methods thereof

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Suwon-si, South Korea

Daehyun Kwon