Samsung Electronics Co., Ltd.

Daehyun Chung

Seungjun Bae

Kwangil Park

JinGook Kim

Jaehyung Lee

Sihong Kim

An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed.

Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices

A memory system may include an integrated circuit memory device and a memory controller coupled to the integrated circuit memory device. The integrated circuit memory device may include a memory cell array having a plurality of memory cells, a clock generator configured to generate a clock signal, a plurality of data input/output buffers, and a delay circuit. The plurality of data input/output buffers may be coupled between respective data input/output pads and the memory cell array, and each of the data input/output buffers may be configured to communicate data with the memory cell array responsive to the clock signal with the clock signal being applied to a clock input of each of the input/output buffers. The delay circuit may be coupled between the clock generator and a first one of the data input/output buffers so that the clock signal is delayed by different amounts at clock inputs of the first data input/output buffer and a second one of the data input/output buffers. Moreover, the memory controller may be configured to perform data training. Related methods and memory devices are also discussed.

Integrated circuit memory devices including delayed clock inputs for input/output buffers and related systems and methods

An integrated circuit device may include an amplifier having an amplifier input configured to receive an input signal with the amplifier being configured to provide an amplifier output signal at an amplifier output responsive to the input signal received at the amplifier input. A capacitor may be coupled to the amplifier output, and a buffer may be coupled to the capacitor so that the capacitor is coupled in series between the amplifier output and an input of the buffer with an output of the buffer being coupled to a buffered signal terminal. A variable resistive feedback circuit may be coupled between the input and output of the buffer with the variable resistive feed back circuit providing a variable resistance between the input and output of the buffer. A feedback resistance controller may be coupled to the variable resistive feedback circuit with the feedback resistance controller being configured to select a first resistance for the variable resistive feedback circuit for a first frequency of the input signal and to select a second resistance for the variable resistive feedback circuit for a second frequency of the input signal different than the first frequency with the first and second resistances being different.

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Gyeonggi-do, South Korea

Daehyun Chung