Samsung Electronics Co., Ltd.

Daehan Kim

Minkyung Lee

Keewon Kim

Wontaeck Jung

Myungnam Lee

Woojin Lee

Sanghoon Ahn

Junghoo Shin

Gyu-Ha Park

Nari Lee

Junhyuk Lim

Gyuha Park

Jeongyeol Kim

A method of detecting, by a nonvolatile memory system, a defective memory cell block from among memory cell blocks, includes performing, after performing an erase operation, a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage that distinguishes an off-cell on which no data is written from an on-cell on which data is written; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage from among the memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of counted hard off-cells.

Nonvolatile memory device and method of detecting defective memory cell block of nonvolatile memory device

Disclosed are an apparatus for and a method of manufacturing a semiconductor device. The apparatus includes a chamber, an evaporator that evaporates an organic source to provide a source gas on a substrate in the chamber, a vacuum pump that pumps the source gas and air from the chamber, an exhaust line between the vacuum pump and the chamber, and an analyzer connected to the exhaust line. The analyzer detects a derived molecule produced from the organic source and determines a replacement time of the evaporate.

Apparatus for and method of manufacturing semiconductor device

A non-volatile memory device includes: one or more memory blocks including a plurality of memory cells connected to a plurality of word lines, and a plurality of memory cell strings; a page buffer unit; one or more pass units including a plurality of pass transistors that may supply operation voltages to the plurality of word lines; one or more monitoring units including one or more monitoring pass transistors connected to the plurality of pass transistors; a voltage generator that may supply activation voltages to a first pass transistor, in which a leakage current is to be measured, and to the one or more monitoring pass transistors; and a control logic that may control the voltage generator to generate the activation voltages by using a voltage control signal and detect the leakage current based on monitoring voltages output from the one or more monitoring pass transistors.

Non-volatile memory device

Disclosed is a nonvolatile memory device which includes a memory cell array, a row decoder circuit that selects one wordline as a target of a program operation, a page buffer circuit that stores data to be written in memory cells connected with the selected wordline in the program operation, and a pass/fail check circuit that determines a pass or a fail of the program operation. In the program operation, the pass/fail check circuit detects a first program speed of first memory cells and a second program speed of second memory cells, and determines a program fail based on the first program speed and the second program speed.

Nonvolatile memory device and storage device including nonvolatile memory device

Disclosed are an apparatus for and a method of manufacturing a semiconductor device. The apparatus includes a chamber, an evaporator that evaporates an organic source to provide a source gas on a substrate in the chamber, a vacuum pump that pumps the source gas and air from the chamber, an exhaust line between the vacuum pump and the chamber, and an analyzer connected to the exhaust line. The analyzer detects a derived molecule produced from the organic source and determines a replacement time of the evaporator.

An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.

Growing community of inventors

Suwon-si, South Korea

Daehan Kim