Samsung Electronics Co., Ltd.

Dae-Young Kwak

Seung-Jae Lee

Sang-Jin Hyun

Min Soo Kim

Jin-wook Lee

Dong-Hyun Roh

Kyu-Tae Na

Ju-Wan Kim

Il-Woo Kim

Jung-Chan Lee

Min-chan Gwak

Ji-ye Kim

Jung-hwan Chun

Seung-Bae Park

Bo-un Yoon

Yu-Gyun Shin

Cheol Kyu Kim

Sang-Bom Kang

Sangjin Hyun

Ki-Hyung Ko

Koungmin Ryu

Yoo-Jung Lee

Byung-Suk Jung

Guyoung Cho

Kyung-Seok Oh

Shinhye Kim

Jae-Sung Hur

An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Method of forming an integrated circuit device having a contact capping layer

Integrated circuit device having fin-type active

A semiconductor device includes active patterns protruding from a substrate and an insulation structure surrounding lower portions of the active patterns. The insulation structure includes an insulation layer conforming to a top surface of the substrate and to sidewalls of the active patterns and a buried insulation pattern on the insulation layer.

Semiconductor device

A semiconductor device is provided as follows. A first fin-type pattern is disposed on a substrate. A first field insulating film is adjacent to a sidewall of the first fin-type pattern. A second field insulating film is adjacent to a sidewall of the first field insulating film. The first field insulating film is interposed between the first fin-type pattern and the second field insulating film. The second field insulating film comprises a first region and a second region. The first region is closer to the sidewall of the first field insulating film. A height from a bottom of the second field insulating film to an upper surface of the second region is larger than a height from the bottom of the second field insulating film to an upper surface of the first region.

Semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device includes forming gate structures on PMOS and NMOS transistor regions of the semiconductor substrate, forming epitaxial blocking layers on source/drain regions of PMOS and NMOS transistor regions using a nitridation process, then selectively removing one of the epitaxial blocking layers, and using a SEG process to form an epitaxial layer on respective source/drain regions while shielding the other source/drain regions with a remaining epitaxial blocking layer.

Method of fabricating semiconductor device including forming epitaxial blocking layers by nitridation process

A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.

Method of manufacturing semiconductor device

An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.

Isolation layer structure, method of forming the same and method of manufacturing a semiconductor device including the same

Method of forming isolation layer structure and method of manufacturing a semiconductor device including the same

Growing community of inventors

Seongnam-si, South Korea

Dae-Young Kwak