Electronics and Telecommunications Research Institute

Dae-Yong Kim

Sang-gi Kim

Jong-dae Kim

Jin-gun Koo

Hyun-Tak Kim

Sang-Pil Han

Min Sang Park

Dong-Hun Lee

Sun-Jin Yun

Hyun-Kyu Yu

Cheon-Soo Kim

Bong-Jun Kim

Han-Cheol Ryu

Kyung-Hyun Park

Jeong-Woo Park

Jin-Hyo Lee

Kyu-Hong Lee

Won-Gu Kang

Nam-Je Kim

Hyun-Sung Ko

Chung-Hwan Kim

Ki-Won Moon

Disclosed herein is a photomixer and method of manufacturing the photomixer which can fundamentally solve the existing restrictive factors of a PCA and a photomixer which are core parts of a conventional broadband terahertz spectroscopy system. The presented photomixer includes an active layer formed on a top surface of a substrate, the active layer being formed on an area on which light is incident, and a thermal conductive layer formed on the top surface of the substrate, the thermal conductive layer being formed on an area other than the area on which light is incident. The active layer is formed to have a mesa cross section, and the thermal conductive layer is regrown on an area other than the area on which light is incident using an MOCVD method, and has a flattened surface.

Photo mixer and method for manufacturing same

Provided are a MIT device self-heating preventive-circuit that can solve a self-heating problem of a MIT device and a method of manufacturing a MIT device self-heating preventive-circuit integrated device. The MIT device self-heating preventive-circuit includes a MIT device that generates an abrupt MIT at a temperature equal to or greater than a critical temperature and is connected to a current driving device to control the flow of current in the current driving device, a transistor that is connected to the MIT device to control the self-heating of the MIT device after generating the MIT in the MIT device, and a resistor connected to the MIT device and the transistor.

Circuit for preventing self-heating of metal-insulator-transition (MIT) device and method of fabricating integrated-device for the same circuit

A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Semiconductor power integrated circuit

Method for fabricating semiconductor power integrated circuit

A method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopants into the substrate, and forming a dielectric layer on a resultant structure to fill the entrance of the trenches, thereby forming air-gap layers inside the trenches, thereby reducing a parasitic capacitance and a magnetic coupling.

Integrated inductor device and method for fabricating the same

A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

Vertically stacked bipolar dynamic random access memory

Growing community of inventors

Daejeon, South Korea

Dae-Yong Kim