Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Pantech Co., Ltd.

Other

Dae-Yong Kim

Sang-Woo Lee

Byung-Hee Kim

Chul-Sung Kim

Eun-Ok Lee

Jun-yong Park

Sang-Bom Kang

Jang-Hee Lee

Sang-Won Hwang

Hyo-Seok Choi

Jeong-Ik Kim

Chung-Hwan Shin

Je-Hyung Ryu

Gil-heyun Choi

Gyu-Hyeong Cho

Yongjin Lee

Hyun-Su Kim

Sangho Kim

Min-sang Song

Kwang-jin Moon

Woong-hee Sohn

Sungmin Yoo

Eun-ji Jung

Sang-Ho Kim

Du-Eung Kim

Yu-Gyun Shin

Hee-Sook Park

Jin-bum Kim

Eun-Ji Jung

Jae-Hwa Park

Young-Ho Suh

Kyung-In Choi

Bo-Geun Kim

Junhyeok Yang

Se-Ki Kim

Joon-Gon Lee

Jong-ho Yun

Kwang-Young Lee

Dong-Hun Heo

JuHwa Kim

Hyun-soo Kim

Sung-ho Han

Seung-Hee Son

Choung-Keun Kwak

Huy Hieu Nguyen

A pet exercise apparatus includes: a base module; a running module which has an exercise space formed therein in an axial direction and an inner circumferential surface or outer circumferential surface rotatably coupled to the base module; and an LED module provided in the base module or the running module to irradiate LED light to the exercise space. The pet exercise system may further includes: a rotary module which has an exercise space part formed therein as a space in which the pet may exercise and a gaze inducing part provided on an inner circumferential surface and inducing a pet's gaze so that the pet continuously moves in the exercise space part and may exercise; a support module supporting the rotary module so that the rotary module is rotatable according to the motion of the pet; a control module controlling an operation of the gaze inducing part; and a terminal including a communication part transmitting an operation control signal CI of the gaze inducing part to be transmitted to the control module.

Pet exercise apparatus and pet exercise system

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Semiconductor devices with shaped portions of elevated source/drain regions

A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage.

Low dropout voltage (LDO) regulator including a dual loop circuit and an application processor and a user device including the same

A reconfigurable bipolar output charge pump circuit includes an input terminal configured to receive an input voltage. First and second terminals are connected to a first flying capacitor, and third and fourth terminals are connected to a second flying capacitor. First and second output terminals are respectively connected to first and second output capacitors and configured to respectively provide a positive output voltage and a negative output voltage. A switch network includes switches configured to connect the input terminal, the first to fourth terminals, and the first and second output terminals to each other in response to switch control signals. The switch network is configured to provide one of multiple potential charge pump modes. A controller generates the switch control signals in response to a mode control signal indicating one of the charge pump modes so that a magnitude of the positive output voltage and the negative output voltage becomes one of multiple predefined voltage levels.

Reconfigurable bipolar output charge pump circuit and integrated circuit including the same

A power path controller included in a system-on-chip (SoC) is provided. The power path controller is coupled to a first power source and a second power source. The power path controller includes a first switch located between the first power source and a memory core included in the SoC, a second switch located between the second power source and the memory core, a comparator configured to compare a first power supply voltage supplied from the first power source with a second power supply voltage supplied from the second power source, and a switch controller configured to selectively activate the first switch or the second switch according to a comparison result of the comparator.

Power path controller of a system-on-chip

A voltage regulator includes a pass element, a buffer, and an error amplifier. The voltage regulator further includes a fast push-pull driver that has an inverter type amplification structure, is connected between a power output and a control input of the pass element, and reduces positive and negative peaks of the power output at a speed faster than a speed of a main feedback loop.

Dual loop voltage regulator based on inverter amplifier and voltage regulating method thereof

A memory controller of inventive concepts may include an active regulator configured to operate in an active mode and be inactive in a sleep mode, an active logic configured to receive a drive voltage, a power gating switch configured to connect the active regulator to the active logic after a transient state of the active mode, the transient state being an initial time period of the active mode, and a charging circuit configured to charge the active logic during the transient state.

Voltage regulator, memory controller and voltage supplying method thereof

Methods of forming semiconductor devices with metal silicide using pre-amorphization implants

A mobile communication terminal having an image conversion function arranges and displays area-specific images in a three-dimensional (3D) space on the basis of distance information of the area-specific images of a two-dimensional (2D) image.

Mobile communication terminal having image conversion function and method

A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

Method of fabricating semiconductor device

A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.

Methods of forming wiring structures

A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.

Semiconductor device and method of manufacturing the same

Growing community of inventors

Yongin-si, South Korea

Dae-Yong Kim