Samsung Electronics Co., Ltd.

Dae-yeong Lee

Dong-Hee Han

Jong-Lae Park

Ju-hwan Kim

Bum-gyu Park

Dong-hyeon Ham

In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Apparatus, method, and system for power consumption management of system-on-chip

There is provided a method of operating a computing device including a processing component based on power consumption. The method includes: obtaining power mode information about the processing component, measuring a temperature of the processing component and a current that flows through the processing component in response to the obtaining the power mode information, generating leakage power information based on the power mode information and the measured temperature and current, and storing the generated leakage power information in a memory.

Computing device and method of operating the same

An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.

Growing community of inventors

Hwaseong-si, South Korea

Dae-yeong Lee