Freescale Semiconductor,inc.

Dae Y Hong

James W Miller

Burton Jesse Carpenter

Tu-Anh N Tran

Mark Allen Gerber

Nhat Dinh Vo

Sohrab Safai

Kendall Dewayne Phillips

A pad () is electrically connected to a first I/O cell () while also physically overlying active circuitry of a second I/O cell (). Note that although the pad () overlies the second I/O cell (), the pad () is not electrically connected to the I/O cell (). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g.-) may have a finer pitch than the corresponding pads (-and-). In addition, the size of the pads may be increased (e.g. padmay be bigger than pad) while the width 'c' of the I/O cells (-) does not have to be increased. Such a pattern (e.g.) may be arranged so that the area required in one or more dimensions may be minimized.

Integrated circuit having pads and input/output (I/O) cells

A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.

Multi-die semiconductor package

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Austin, TX, United States of America

Dae Y Hong