Samsung Electronics Co., Ltd.

Dae-Woong Kim

Hyun-Woong Lee

Soo-woong Lee

Min Soo Kim

Cheol-Ho Lee

Il-Hyung Chung

Soo-Wong Lee

Jong-In Kim

Young-wook Jang

Kwan-Ho Kim

Young-Joon Kim

Bong-chun Kang

Dong-Ho Yu

Hyun Woong Lee

Kyu-Yull Yi

An electronic device and a method for changing modes according to external devices connected through a universal serial bus (USB) and controlling the strength of signals communicated according to changed modes are provided. The method includes detecting a connection with an external device corresponding to booting of the electronic device, determining a mode of the electronic device according to the detected connection with the external device, varying a characteristic setting of an input output (IO) buffer to a certain strength corresponding to the determined mode, and communicating a signal at a strength corresponding to the varied setting.

Electronic device and method for controlling signal strength according to mode

The present disclosure relates to an improvement in the quality of a transmitted signal, and more particularly, to an electronic apparatus and a method which are provided with a passive equalizer improving the quality of a transmitted signal when a signal is transmitted/received to/from an external apparatus, and a system for the same. The present disclosure provides a signal transmission system for improving the quality of a transmitted signal. The signal transmission system may include a transmitter that transmits a signal; a receiver that receives the signal from the transmitter; a channel that is formed between the transmitter and the receiver and transmits the signal delivered by the transmitter; and a passive equalizer that is formed between the transmitter and the receiver and controls the signal so as to have a higher impedence than a predetermined impedance at a lower frequency than a predetermined frequency of the signal.

Electronic apparatus and method for improving quality of transmitted signal, and system for the same

An on-chip clock controller includes a clock-control chain configured to shift first clock-control bits in serial and output the first clock-control bits to a first clock domain in parallel in response to a clock-control scan clock provided from outside of a chip, and a first domain clock generator, the first domain clock generator configured, during a test mode, to generate a first internal clock by selectively outputting a first data scan clock provided from outside of the chip or a first functional clock generated from inside of the chip.

On-chip controller and a system-on-chip

A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.

Memory controller

A data coding apparatus and method for recording digital data on a storage device are provided, where the recording apparatus reduces the number of times that memory is accessed by storing only additional information and parity information when ECC encoded data are temporarily stored in an external memory, and performs data coding without any clock loss by scrambling only a specific field on-the-fly when the data stored in the external memory are read.

Digital data coding and recording apparatus, and method of using the same

Provided are a recording medium, a recording medium playing device and method, which has an EFM demodulation unit for adaptively realigning an EFM demodulation point. The recording medium demodulates first data into second data in response to a channel clock signal recovered from the first data, compares a demodulation point indicating demodulation of the first data into the second data with an alignment point set in response to the first data, and jumps the demodulation point forward or backward by a difference between the demodulation point and the alignment point.

Recording medium having EFM demodulation unit for adaptively re-aligning EFM demodulation point, device and method for playing the same

An on-the-fly error checking and correcting system and method of supporting a non-volatile memory processes data using an on-the-fly error correction method to be performed between a temporary memory and a flash memory. The flash memory stores actual data read from the temporary memory and parity generated on-the-fly in a write mode, and transmits the stored data to the temporary memory, computes a syndrome from the stored data on-the-fly, and generates an error correction information signal according to the result of computing in a read mode. Thus, error correction may only be selectively performed.

On-the fly error checking and correction CODEC system and method for supporting non-volatile memory

Optical disk players include a disk spinning system that is configured to spin an optical disk at a constant linear velocity and a burst cutting area decoding system that is configured to decode data in a burst cutting area of the optical disk, while the optical disk is spinning at the constant linear velocity. The burst cutting area data decoding system may be configured to determine a rotational frequency of the optical disk while reading the data in the burst cutting area, and using the rotational frequency that was determined to decode the data in the burst cutting area that was read.

Optical disk players and methods for detecting burst cutting area (BCA) data in a constant linear velocity mode

A nonvolatile memory device and a method of manufacturing the same are provided. An insulation layer having a high etching rate as compared with a pad oxide layer is formed as a buffer layer between a first STI film formed as a lower part of semiconductor substrate and a second STI film formed as an upper part of the semiconductor substrate, to obtain a pillar CD for an SAP structure. The buffer layer is etched more speedily in comparison with the pad oxide layer in a procedure of etching the pad oxide layer, thus ensuring a sufficient pillar CD without an excessive wet etch-back. Accordingly, a defect occurrence such as a grooving or seam can be prevented in realizing the SAP structure, and a tunnel oxide layer can be formed with uniform thickness.

Nonvolatile memory device

A method of forming an isolation layer structure for a semiconductor device includes forming a first structure on a substrate, the first structure including an insulation layer pattern having a sacrificial pattern therein, the sacrificial pattern having an etching rate that is different from the insulation layer pattern, partially removing the insulation layer pattern until the sacrificial pattern is exposed to form a second structure, partially removing the sacrificial pattern from the insulation layer pattern to form a third structure having a recessed portion at a central portion thereof, and removing an upper portion of the third structure such that a top surface of the third structure is concave with respect to a top surface of the substrate.

Method of forming an insulation layer structure having a concave surface and method of manufacturing a memory device using the same

A data coding apparatus and method for recording digital data on a digital versatile disk (DVD) are provided, where the DVD recording apparatus reduces the number of times that memory is accessed by storing only additional information and parity information when ECC encoded data are temporarily stored in an external memory, and performs data coding without any clock loss by scrambling only a specific field on-the-fly when the data stored in the external memory are read.

Digital data coding apparatus, DVD recording apparatus, and method of using the same

Provided are a restoration system and method for an optical disc, by which a radio frequency signal optically picked up from an optical disc is restored. The restoration system includes a slice, a phase locked loop, a latch circuit, a 3T correction circuit, and a demodulator. In particular, the 3T correction circuit includes an extension storage device, a length measuring device, a phase detector, and an extension determiner and corrects data output from the extension storage device. In the restoration method, data required for determining the need for correction and the direction of correction is detected and a plurality of steps for selecting non-correction, two directional correction, forward correction, and backward correction are performed, thereby correcting the high radio frequency signal according to conditions of the high radio frequency signal. It is preferable that the restoration system operates according to the restoration method.

System and method for restoring an optical disc signal

A frame synchronization signal detection apparatus includes a synchronization signal detector, a main frame synchronization signal generator, a sub frame synchronization signal generator, and an output unit. The synchronization signal detector detects and outputs a synchronization signal from a digital data signal. The main frame synchronization signal generator detects and outputs a first valid synchronization signal from the synchronization signal, as an internal frame synchronization signal, and generates and outputs a first insertion synchronization signal, as the internal frame synchronization signal, if the first valid synchronization signal is not detected in a predetermined first time period. The sub frame synchronization signal generator detects and outputs a second valid synchronization signal from a synchronization signal. The output unit outputs a frame synchronization signal. The main frame synchronization signal generator stops generating the first insertion synchronization signal, and detects and outputs a first valid synchronization signal as an internal frame synchronization signal.

Apparatus and method for detecting frame synchronization signal for reducing errors in data demodulation in optical disc system

An apparatus and a method for scrambling and descrambling data wordwise in an optical disk system are provided. The apparatus includes a bit storing means which stores at least 15 bits, and a calculating means which calculates first through fifteenth bits of the bit storing means in parallel during one clock cycle and inputs the results of the calculation back into the bit storing means. The calculating means performs an XOR logic operation on a seventh bit and a fifteenth bit, on a first bit, an eighth bit, and a twelfth bit, on a second bit, a ninth bit, and a thirteenth bit, on a third bit, a tenth bit, and a fourteenth bit, on a fourth bit, an eleventh bit, and a fifteenth bit, on the first bit and a fifth bit, on the second bit and a sixth bit, on a third bit and the seventh bit, on the fourth bit and the eighth bit, on the fifth bit and the ninth bit, on the sixth bit and the tenth bit, on the seventh bit and the eleventh bit, on the eighth bit and the twelfth bit, on the ninth bit and the thirteenth bit, and on the tenth bit and the fourteenth bit, and inputs the results of the XOR logic operations into the bit storing means.

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Seoul, South Korea

Dae-Woong Kim