Samsung Electronics Co., Ltd.

Dae-Woong Kang

Sung-Nam Chang

Eun-Jung Lee

Jong-Sun Sel

Bong-Tae Park

Jin-joo Kim

Kyong-Joo Lee

Jung-Dal Choi

Kyu-Charn Park

Hong-Soo Kim

Seong-Soon Cho

Yong-Sik Yim

Kwang-jae Lee

Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap.

Semiconductor devices comprising a plurality of gate structures

Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.

A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.

Non-volatile memory devices including fuse covered field regions

A non-volatile memory device including a barrier spacer that serves to protect a control gate, including a metal layer, from damage that may result from exposure to a cleaning solution and/or oxygen. With the barrier spacer layer, a cleaning process using a high-power cleaning solution may be used to effectively remove etch byproducts. An oxidation process may be performed to cure etch damage of an intergate dielectric pattern, a floating gate and a gate insulator. The barrier spacer and/or the oxidation process enable a non-volatile memory device having enhanced speed and reliability to be formed.

Non-volatile memory devices and methods of forming non-volatile memory devices

Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

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Seoul, South Korea

Dae-Woong Kang