National Semiconductor Corporation

Dae Woon Kang

James Thomas Doyle

Martin Dermody

A system and method is disclosed for providing a robust ultra low power serial interface with a digital clock and data recovery circuit for power management systems. In one advantageous embodiment a digital clock and data recovery circuit of the invention comprises a quadruple phase clock generator circuit that generates four shifted clock signals, a decision logic circuit, a state detector circuit, and an edge detector circuit. The detected edges of data signals are used to latch the state of the four shifted clock signals. The state detector circuit selects a stable clock signal among the four shifted clock signals for use as a recovered clock signal and synchronizes the recovered clock signal at a center of the data signal. The selected recovered clock signal remains available until another data signal transition is detected.

System and method for providing a robust ultra low power serial interface with digital clock and data recovery circuit for power management systems

The present invention provides a versatile system for management of clocking for a serial interface. Serial input data, comprising a plurality of fields, and preceded by a specific input pattern, is provided to a receiver element. Within one of the fields in the serial input data, some information concerning the size the current serial data payload is included. Responsive to receiving the specific input pattern, the system of the present invention asserts a clock enable signal to activate clocking. A countdown corresponding to the size the current serial data payload is initiated. Once that countdown has reached zero, the clocking for the interface is disabled.

Versatile clock management system for a single pin serial interface protocol

A method for operating a power controller in a wireless communication device is provided that includes generating a power controller output signal using an open loop polar modulation scheme. The power controller output signal is operable to control the power delivered to a high-band power amplifier and a low-band power amplifier. A band state is determined for the wireless communication device. The power controller output signal is provided to the high-band power amplifier when the band state is a high-band state and to the low-band power amplifier when the band state is a low-band state.

System and method for providing a power controller with flat amplitude and phase response

A system and method is disclosed that provides a digital self-adjusting power supply for semiconductor digital circuits. The power supply provides a substantially constant minimum supply voltage with regard to process corner, junction temperature, external voltage source, load variation, and operating frequency. The system comprises a slack time detector, a voltage adjuster, and a digital pulse width modulation (PWM) modulator. The system supplies a minimum required voltage without the used of a band gap or reference voltage. A finite state machine is also used to minimize oscillations introduced by start-up, load transients, frequency changes, and the like, thereby eliminating the need for a proportional integrator differentiator (PID) circuit.

System and method for providing a digital self-adjusting power supply that provides a substantially constant minimum supply voltage with regard to variations of PVT, load, and frequency

On-chip AC noise suppression is provided for a target circuit within an integrated circuit chip. A power supply line filter is provided in the power supply line that feeds the target circuit. The filter includes a polysilicon resistor formed over a charged substrate well, with a dielectric material interposed between the well and the resistor. This decreases capacitive coupling between the substrate and the resistor, thereby suppressing AC noise that is injected via the substrate. For an on-chip bandgap reference circuit, AC noise suppression can be achieved by providing matched AC impedances in the PTAT and inverse PTAT branches of the circuit. This technique exploits the common-mode rejection capability of the error amplifier within the bandgap reference circuit. Also, the inputs of the error amplifier can be capacitively coupled together to exploit the amplifier's common-mode rejection capability for the suppression of AC noise that is injected at the amplifier inputs.

Integrated circuits with on-chip AC noise suppression

A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

Circuit and method for digital delay and circuits incorporating the same

A method and apparatus for dividing the frequency of an input clock signal by an odd integer is disclosed. The output of two asymmetrical clock dividers may be combined to produce a divided clock signal having a symmetrical waveform. Finite state machines may be used as asymmetrical clock dividers having desired duty cycles and relative turn-on and turn-off times to produce signals that combine to form a symmetrical divided clock signal. Alternatively, the output of an asymmetrical clock divider may be delayed by one input clock signal half-cycle and combined with the original asymmetrical signal to form a symmetrical divided clock signal.

Method and apparatus for a symmetrical odd-number clock divider

A circuit for providing an output current is provided. The circuit includes a differential amplifier, a transistor having a gate that is coupled to the output of the differential amplifier, a comparator, and a sense resistor that is coupled between the drain of the transistor and the input pin. One input of the differential amplifier is connected to the input pin and the other input is connected to a reference voltage. The inputs of the comparator are coupled across the sense resistor. If an external resistor is coupled to the input pin, the comparator trips. If the comparator is tripped, the current from the external resistor is mirrored to provide the output current. If the comparator is not tripped, the output current is provided from an on-chip current source.

Apparatus and method for single pin current-programmable multi-function/multi-purpose selector

The performance of a bandgap reference circuit is improved by increasing the &#x394;VBE, and thereby correspondingly decreasing the input sensitivity of the error amplifier in the control loop. The &#x394;VBE can be increased by presenting stacked diode configurations at the amplifier inputs, by increasing the diode ratio presented at the amplifier inputs, and by providing a higher current in the CTAT leg than in the PTAT leg. The stacked diode configuration is achieved by producing isolated diodes with a triple well CMOS process. The stacked diode configuration and the triple well CMOS process also permit the input stage of the amplifier to use N-channel transistors operating in the threshold region.

Bandgap reference designs with stacked diodes, integrated current source and integrated sub-bandgap reference

A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal based on the at least one selected version of the second signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

An all digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes an up/down counter and a pulse width modulator to output a signal into a LC network that generates the supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal. The system supplies the optimum or minimum required voltage to insure that a critical path through a digital chip is met over process, voltage, and temperature (PVT) variations without the use of a band gap reference voltage source. A state machine is also used to counteract oscillations introduced by start up and load transients, thereby eliminating the need for a proportional integrator differentiator (PID).

All digital power supply system and method that provides a substantially constant supply voltage over changes in PVT without a band gap reference voltage

Growing community of inventors

Boulder, CO, United States of America

Dae Woon Kang