Samsung Electronics Co., Ltd.

Dae-Wook Kim

Jun-Jin Kong

Nam-Shik Kim

Bi-woong Chung

Tae-Hwan Kim

Hong-Rak Son

Jin-Young Lee

Ja-hum Ku

Man-Keun Seo

Sung-won Choi

Sang-Jin Choi

Chang-Ho Han

Han-Hum Park

Byoung-Hoon Kim

A processing method includes processing a wafer based on initial data, measuring errors for each of the plurality of areas, calculating an error similarity of at least some of the plurality of areas as a function of a separation distance between each pair of some of the areas, selecting a first area and a plurality of second areas adjacent to the first area, calculating weight values for the second areas based on the error similarities between each pair of second areas and the error similarities between the first area and each second area, calculating an estimated error of the first area based on the measured errors of the second areas and the weight values for the second areas, and generating estimated data based on the estimated errors for each of the plurality of areas.

Method of calibrating target values and processing systems configured to calibrate the target values

Provided are data compression method, data compression apparatus, and memory system. The data compression method includes receiving input data and generating a hash key for the input data, searching a hash table with the generated hash key, and if it is determined that the input data is a hash hit, compressing the input data using the hash table; and searching a cache memory with the input data, and if it is determined that the input data is a cache hit, compressing the input data using the cache memory.

Data compression apparatus, data compression method, and memory system including the data compression apparatus

A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.

Method of operating cyclic redundancy check in memory system and memory controller using the same

A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

Hard-decision decoding method and low-density parity-check decoder using same

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Osan-si, South Korea

Dae-Wook Kim