Skhynix Inc.

Hyundai Motor Company

Kia Motors Corporation

Doors Korea Co., Ltd.

Intel Corporation

Lg Electronics Inc.

Borgwarner Inc.

Hl Mando Corporation

Institute for Advanced Engineering

Korea Western Power Co., Ltd.

Gmarket Inc.

Dae Sung Kim

Back Sik Kim

Kyoung Pyo Ha

Dong Hee Han

Ingee Suh

Hyung Ick Kim

Myungsik Choi

Soon Young Kang

Wootae Kim

Woo Tae Kim

Jang Seob Kim

Myung Jin Jo

Jae Hyeong Jeong

Kwang Hyun Kim

Chol Su Chae

Sung Ho Ahn

Sang Ho Yun

Wan Je Sung

Bi Woong Chung

Yooshin Cho

Jae Yong Son

Chung Han Oh

Chun Woo Lee

Sang Gon Lee

Kyung Bum Kim

In Gee Suh

Eui Chul Choi

Bo Seok Jeong

Hyun Jun Lee

Woo Hyuck Chang

Joong Soo Kim

Min Su Choi

Soo Hyung Woo

In Sang Ryu

Jin Wook Lee

Byong Young Choi

Seung Gu Ji

Sung Hoon Lee

Seung Cheol Lee

Won Gyu Kim

Hoon Young Cho

Nam Kyeong Kim

Ethan Benjamin Rubinson

Seung Kook Han

Mun Soon Kwon

Won Gyu Shin

Jung Hee Ryu

Sang Sik Kim

Hong Wook Lee

Hyuk Im

Myung Rae Cho

Hyun Cheol Bae

Duk Jin Park

Hosung Cho

Seung Jong Lee

Seong Hyuk Kang

Taewon Park

Sang Hee Lee

Ki-Young Kwon

Gang Il Kim

Jae Young Han

Sung Han Kang

Won Seon Sim

Won-Jung Kwon

Min Jae Kang

Jung Ae Lee

Sang Seob Lee

Jin Gyu Yang

Jin Woo Yang

Byeong Seok Lee

Jai Hyun Ahn

Ji Hee Cheon

Young-Taek Sun

Kwangsoon Choi

Seong Gwon Jeong

Sin Ho Yang

Do Kyung Kang

Sang Oh Nam

Hyun Woo Jin

Dae Min Kim

Hyuk Min Kwon

Dae Yoon Oh

Hyung-Ick Kim

WooTae Kim

Yongseung Yun

Seok Woo Chung

Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.

Memory controller and memory system including the same

A memory device may include a read controller and an error correction circuit. The read controller may sequentially perform a plurality of read retry operations on a memory device. The error correction circuit may perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and perform a second error correction decoding based on read data corresponding to a minimum USC value among the plurality of USC values.

Memory controller performing error correction and operating method thereof

A storage device may include a memory device and a memory controller. The memory device may store data. The memory controller may iterate error correction decoding on data read from the memory device, determine whether to continue iterating based on a result obtained by comparing a first threshold number with a number of Unsatisfied Check Nodes (UCNs) included in a syndrome of first decoded data, which is a result of a first set number of iterations of the error correction decoding on the read data, and determine whether to continue iterating based on a result obtained by comparing a second threshold number with a number of UCNs included in a syndrome of second decoded data, which is a result of a sum of the first set number and a second set number of iterations of the error correction decoding on the read data.

Error correction decoder, storage device including error correction decoder, and operating method thereof

A storage device includes a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and a controller configured to control the memory and perform a read retry operation for the memory using a read retry table. The memory includes a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions.

Memory control circuit providing die-level read retry table, memory package, and storage device

The present technology provides a controller for controlling a memory device comprising: a hard syndrome calculator configured to generate a hard syndrome of a hard data chunk received from the memory device; a delta syndrome calculator configured to generate a delta syndrome of a delta bit data received from the memory device, the delta bit data indicating a reliability of the hard data chunk; a soft syndrome generator configured to generate a soft syndrome of the hard syndrome and the delta syndrome; a data determinator configured to select, as hard decision data, one of the hard data chunk and a soft data chunk, the selected data chunk corresponding to a syndrome having a lowest syndrome weight; and an error corrector configured to perform an ECC decoding operation on the hard decision data.

Electronic device having ECC decoder

A decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. The decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.

Decoding device for determining whether to decode data unit, and operating method thereof

A controller and an operating method of the controller may calculate a first syndrome weight which is syndrome weight for first read data, calculate a second syndrome weight which is syndrome weight for second read data, and determine first reliability data and second reliability data based on the first syndrome weight and the second syndrome weight. The first read data may be read from a memory area using a first read bias and the second read data may be read from the memory area using a second read bias different from the first read bias.

Controller and operating method of the controller for determining reliability data based on syndrome weight

A method of manufacturing a semiconductor memory device includes alternately stacking sacrificial layers and interlayer insulating layers over a lower structure, forming a slit passing through the sacrificial layers and the interlayer insulating layers, removing the sacrificial layers through the slit through a wet etching process, and removing, through a dry etching process, a byproduct that is produced at ends of the interlayer insulating layers during the wet etching process.

Manufacturing method of semiconductor memory device

A memory system includes a memory device and a controller. The memory device outputs a codeword read from plural memory cells in response to a request. The controller is configured to establish a plurality of variable nodes and a plurality of check nodes from the codeword, perform a second flipping function operation for estimating flipping necessity and flipping frequency regarding the plurality of variable nodes based on the plurality of check nodes, determine, based on the flipping necessity and the flipping frequency, which iterative operation is performed during a first flipping operation for decoding the codeword, and perform the first flipping operation through a determined iterative operation to obtain the plurality of variable nodes.

Apparatus and method for checking an error in a bit-flipping decoder

Techniques for resource allocation with content creators are described that overcome the challenges of conventional techniques by supporting customized digital content generation and resource allocation specified by content creators of digital content. In one example, a content provider system, based on user input received via a control, specifies the portions of a resource allocation to be shared. A first portion is configured to be shared with a content creator of digital content, the digital content including service access data configured to access a digital service. A second portion is also configured to be shared with a client device that utilizes the service access data to access the digital service. Digital content is generated based on the specified portions and is transmitted. Upon access by the client device to the digital service, an indication of receipt of the first portion of the resource allocation is displayed by the content provider system.

Digital service resource allocation and sharing

The present embodiments relate to a steering assist device and method, and a steering system. The steering assist device comprises: first and second input-side steering control modules for controlling an input-side steering motor so that an input-side instrument connected to a steering wheel is assisted; and first and second output-side steering control modules for controlling an output-side steering motor so that an output-side instrument mechanically separated from the input-side instrument and connected to a wheel is assisted, wherein the first and second input-side steering control modules and the first and second output-side steering control modules arbitrate a role assignment and can control a corresponding steering motor from among the input-side steering motor and the output-side steering motor according to the role assignment arbitration result.

Steering assist device and method, and steering system

A controller may include i) a storage memory configured to store N-bit read data and N reliability data units, ii) a decoder configured to execute a decoding operation for the read data based on the reliability data units, and iii) a processing circuit configured to determine a value of reliability data unit corresponding to I-th bit of read data based on an I-th bit of first read data, an I-th bit of second read data and a difference between first syndrome weight and second syndrome weight.

Controller and operating method thereof for determining reliability data based on syndrome weight

A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.

Memory device and memory system

A storage device having improved performance includes: a plurality of memory devices, each memory device including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to be in communication with the plurality of memory devices to provide a read command for instructing a read operation on the plurality of memory blocks to read out data and provide a read enable signal to the memory devices during at least part of an idle time of the channel, which occurs while the read operation is being performed. The plurality of memory devices output first data to the memory controller through the channel in response to the read enable signal, wherein the first data is different from the data previously read out by the read operation that provides the read enable signal in response to the read command.

Data storage device for performing read operation and operating method thereof

Growing community of inventors

Gyeonggi-do, South Korea

Dae Sung Kim