Skhynix Inc.

Hynix Semiconductor Inc.

Dae-Suk Kim

Jong-Chern Lee

Chang-Hyun Lee

Chul Kyu Kim

Jong Chern Lee

Seok-Cheol Yoon

Young-Jun Ku

Tae-Sik Yun

Jin-Hee Cho

Jang-Ryul Kim

No-Guen Joo

A semiconductor memory device includes: a plurality of banks each including a plurality of cell mats and a plurality of sense amplifiers shared by adjacent cell mats; and a bank control circuit suitable for activating a normal word line of a particular cell mat of a bank selected according to a refresh command including bank information, and activating a target word line of a cell mat that does not share a sense amplifier with the particular cell mat according to a target refresh command after a preset delay time.

Semiconductor memory device and operating method thereof

A semiconductor device includes: first to Ninput terminals (where N is an integer equal to or greater than 2); and a redundant input terminal. When a Kinput terminal (where K is an integer ranging from 1 to N&#x2212;1) is defective among the first to Ninput terminals, (K+1)to Ninput terminals receive signals of Kto (N&#x2212;1)input terminals, respectively, and the redundant input terminal receives a signal of the Ninput terminal.

Semiconductor device

A semiconductor device includes a built-in self-test controller suitable for generating a test command and test data, and generating a test result signal in response to test result data, in a built-in self-test mode, an internal circuit suitable for performing a test operation in response to the test command and the test data and generating the test result data as a result of the test operation, and a signal transfer controller suitable for outputting the test command, the test data, and the test result signal through a set probe pad and a set bump pad in the built-in self-test mode.

Semiconductor device that supporting a built-in self-test (BIST) operation and multi-semiconductor package including the same

A memory device may include a plurality of cell arrays, a first interface suitable for inputting/outputting first data between the plurality of cell arrays and a host apparatus, a second interface suitable for inputting/outputting second data between the plurality of cell arrays and a device other than the host apparatus, and a data erasure circuit suitable for erasing the first data of the plurality of cell arrays when a first mode in which the first interface is used switches to a second mode in which the second interface is used.

Memory device and operation method thereof

A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (DLL) suitable for delaying the clock to generate a delay locked clock, a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two, a delay unit suitable for delaying the clock corrected by the DLL by a value corresponding to the digital code to output a delayed clock, and a strobing unit suitable for strobing the input signal using the delayed clock.

Clock phase adjusting circuit and semiconductor device including the same

An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

Integrated circuit for detecting defects of through chip via

An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.

Multi-test apparatus and method for testing a plurailty of semiconductor chips

A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.

Memory and test method for memory

A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.

Setting circuit and integrated circuit including the same

A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.

Semiconductor memory device and method for operating the same

A semiconductor memory device having multiple banks each including multiple memory blocks arranged in column and row directions. The memory blocks are divided into multiple memory block groups each sharing a corresponding column select signal. The memory blocks belonging to the respective memory block groups are arranged adjacently in the column direction. Multiple global input/output lines are separately connected to the memory block groups of the respective banks to transfer data of the memory blocks belonging to the respective memory block groups in a time division manner.

Semiconductor memory device

A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.

Growing community of inventors

Gyeonggi-do, South Korea

Dae-Suk Kim