Sun Microsystems, Inc.

Dae Suk Jung

Yet-Ping Pai

Seong Rai Cho

Yu-Yen Mo

Manoj Gopalan

Kyung T Lee

Venkat R Podduturi

Jiun-Cheng Hsu

A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

Hierarchical repeater insertion

A system is provided that facilitates placing repeating flip-flop stations on signal lines within an integrated circuit. The system operates by first receiving a layout that includes multiple functional blocks, and a netlist that specifies interconnections for signals between these functional blocks. The system determines a transit time for a signal interconnecting the functional blocks. If this transit time exceeds an allowed time, the system divides the interconnection into two or more sections, wherein the transit times on the sections are each less than the allowed time. The system then places a repeating flip-flop station within a channel on the integrated circuit in a position that allows the transit time on these sections to be met. Next, the system routes the signal from the originating functional block through a flip-flop located at the repeating flip-flop station to a receiver at the destination functional block.

Method and apparatus for placing repeating flip-flop stations on signal lines within an integrated circuit

One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.

Method and apparatus for calibrating parameters to be used in a digital circuit simulation

One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.

Growing community of inventors

Santa Clara, CA, United States of America

Dae Suk Jung