Samsung Electronics Co., Ltd.

Dae Sin Kim

Kwang Soo Seol

SeungHyun Lim

Zhiliang Xia

Yonghee Park

Homin Son

Daewoong Kang

Dongwon Kim

Keun Hwi Cho

Hagju Cho

Je Hyun Lee

Sangdeok Kwon

Min Chul Park

Sunghoi Hur

Sung Hee Lee

Jaehun Jung

Ji Yong Park

Sangyong Kim

Chiho Kim

Seungkyu Kim

Changsub Lee

Hyun-Wook Lee

Jeong Hoon Ko

Nambin Kim

Nara Kim

Dong-Gwan Shin

Sat Byul Kim

Joohyung You

Sae Jin Kim

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.

Semiconductor device and method of fabricating the same

A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

Semiconductor device

A method for analyzing a wafer map using a wafer map analyzer includes generating first wafer maps each displaying characteristics of a first wafer for a corresponding channel of a plurality of channels. The first wafer maps are auto-encoded together to extract a first feature. The method also includes determining whether the first feature is a valid pattern, classifying the type of the first feature based on unsupervised learning when the first feature is a valid pattern and extracting a representative image of features classified into the same type as the first feature.

Wafer map analyzer, method for analyzing wafer map using the same and method for manufacturing semiconductor device

Provided are a method and system for analyzing grains using a high-resolution transmission electron microscopy (HRTEM) image. The method relates to analyzing nanometer grains, and includes receiving an HRTEM image, setting local windows each having a predetermined size for the HRTEM image, performing at least one Fast Fourier transformation on pixel data determined by the local windows to calculate local transformation data; and analyzing grains based on the local transformation data.

Grain analyzing method and system using HRTEM image

Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

Non-volatile memory devices including charge storage layers

A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

Vertical memory devices having charge storage layers with thinned portions

A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell.

Method for testing retention characteristics of semiconductor device having a volatile device cell and semiconductor test apparatus

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Hwaseong-si, South Korea

Dae Sin Kim