Samsung Electronics Co., Ltd.

Skhynix Inc.

Dae-Sik Park

Jin-Yub Lee

Se-Han Kwon

Chang-Youn Hwang

Ill-Hee Joe

Do-Hyung Kim

Seung-Bum Kim

Hong-Gu Yi

Noh-Jung Kwak

Yun-Je Choi

Doo-Sung Jung

Ki-Soo Choi

Hae-Jung Park

Sang-Kil Kang

Hwa-Chul Lee

Young-Joon Choi

Tae-Gyun Kim

Seong-Kue Jo

Seok-Heon Lee

Seok-Heon Samsung Electronics Taiwan Co Ltd Lee

Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Semiconductor device including air gaps and method for fabricating the same

A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Semiconductor memory device with selectively located air gaps

A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.

Semiconductor device with air gap and method for fabricating the same

Semiconductor device with line-type air gaps and method for fabricating the same

A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic.

Flash memory device capable of preventing soft-programming during a read operation and reading method thereof

An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

Erase voltage generator circuit for providing uniform erase execution time and nonvolatile memory device having the same

A memory device and method thereof are provided. The memory device may comprise a first buffer for receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell; a second buffer for loading LSB data stored in the memory cell; and a data loader for generating at least one load signal based upon logic levels of the received MSB data in the first buffer and the loaded LSB data in the second buffer, the at least one load signal being configured to control programming permissions for the memory cell.

Memory device and method thereof

Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.

Flash memory device having reduced program time and related programming method

A power-voltage driver circuit includes a first MOS transistor configured to turn a second MOS transistor off when a high-voltage generator provides a high voltage output. Related methods are also disclosed.

High-voltage generation circuits and nonvolatile semiconductor memory device with improved high-voltage efficiency and methods of operating

A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

Growing community of inventors

Gyeonggi-do, South Korea

Dae-Sik Park