Samsung Electronics Co., Ltd.

Dae Sik Ham

Sanghun Kim

Jung Ho Lee

Sang-Hyun Joo

Won-Taeck Jung

Jun-Ho Seo

Sang Yong Yoon

Yong-Wan Son

Gi Baek Kim

A memory device includes a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.

Nonvolatile memory device supporting GIDL erase operation

A memory device includes a memory block including a first adjacent word line, a selected word line, and a second adjacent word line provided in a direction perpendicular to a substrate and an address decoding circuit. In a first setup period in which the selected word line is set up, the address decoding circuit is configured to apply a first pre-setup voltage to the first adjacent word line, apply a first setup voltage that is higher than the first pre-setup voltage to the first adjacent word line, apply a second pre-setup voltage to the second adjacent word line, and apply a second setup voltage that is higher than the second pre-setup voltage to the second adjacent word line. The first pre-setup voltage is higher than the second pre-setup voltage.

Memory device for individually applying voltages to word lines adjacent to selected word line, and operating method thereof

A non-volatile memory device including: a first string including a first string select transistor, a first memory cell and a first ground select transistor, a second string including a second string select transistor, a second memory cell and a second ground select transistor, and a controller to apply a pass voltage to a first string select line from a first time, apply a first read voltage to a first word line during a first read section from the first time to a second time, apply a first ground select line voltage to a first ground select line from the first time, apply a ground voltage to a second string select line, apply the first ground select line voltage to a second ground select line during a first control section, and apply a first common source line voltage to a common source line during the first control section.

Non-volatile memory device and an operation method thereof

Growing community of inventors

Suwon-si, South Korea

Dae Sik Ham