Samsung Electronics Co., Ltd.

Dae-Seong Lee

Min-Su Kim

Jong-Kyu Ryu

Hyun-chul Hwang

Chung-Hee Kim

Ji-Kyum Kim

Uk-Rae Cho

Gun-Ok Jung

Yong-Geol Kim

Emil Kagramanyan

Matthew S Berzins

Ah-Reum Kim

Hyun Shik Lee

James Jung Lim

Dae-young Moon

Doo-Seok Yoon

Kyung-bong Kim

An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Integrated circuit including asymmetric ending cells and system-on-chip including the same

A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Semiconductor devices, methods of designing layouts of semiconductor devices and methods of fabricating semiconductor devices

An integrated circuit including standard cells, a method and a computing system for designing and fabricating the same are provided. A computer-implemented method involves placing, based on a standard cell library, standard cells of an integrated circuit to be fabricated, and routing the placed standard cells. A position of a first wiring of a placed cell among the placed standard cells may be adjusted based on a position of a second wiring used for the routing. The first wiring is provided from at least one standard cell, formed in a same layer as that of the second wiring, and spaced from the second wiring in a first direction. An integrated circuit layout having the adjusted position of the first wiring, is produced.

Integrated circuit including standard cell and method and system for designing and manufacturing the same

An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Integrated circuit including multi-height standard cell and method of designing the same

A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

Flip-flop

A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

Multi-bit flip-flops

An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.

Integrated circuit and electronic apparatus including integrated circuit

A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.

Semiconductor integrated circuits

A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.

Semiconductor device, layout system, and standard cell library

Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Growing community of inventors

Busan, South Korea

Dae-Seong Lee