Samsung Electronics Co., Ltd.

Dae Seok Byeon

Jun Jin Kong

Eun Chu Oh

Ji Su Kim

Dong Jin Shin

Ji Sang Lee

Bong Soon Lim

Pan Suk Kwak

Jae Ick Son

Chan Kim

Il Han Park

Chi Weon Yoon

Hyun Jun Yoon

Han Jun Lee

Oh Suk Kwon

Myung Hun Lee

Jin Bae Bang

Seung Hwan Song

Na Young Choi

Young Sun Min

Seung-Jae Lee

Sung Hoon Kim

Jung Hwan Lee

Wook-Ghee Hahn

Dong Ku Kang

Jee Yong Kim

Chang-Bum Kim

Young Ho Lim

Hyun Seok Lim

Tae-hong Kwon

Sung Whan Seo

Kyung Hwa Yun

Jeong Gil Lee

Young Ho Na

Doo Ho Cho

Dong Ha Shin

Kyo Man Kang

Kyung Min Ko

Jung Ho Song

Tae Hong Kwon

A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures.

Nonvolatile memory device with openings in the substrate and nonvolatile memory system including the same

A mold structure includes gate electrodes stacked on a first substrate, a channel structure penetrating a first region of the mold structure to cross the gate electrodes, a first through structure penetrating a second region of the mold structure, and a second through structure penetrating a third region of the mold structure. The mold structure includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell and dummy blocks includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.

Semiconductor memory device with mold structure

A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Non-volatile memory device, operating method thereof, and storage device having the same

A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.

Semiconductor wafer

In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor memory device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

Semiconductor memory device with a plurality of amplification stages

A memory device includes nonvolatile memory cells, and a secure module to process first data including information about the device stored in the cells to generate a first password key, process second data including information about the device stored in the cells to generate a second password key, generate a public key and a secret key by a public-key cryptography algorithm, using the first password key and the second password key, and provide the first password key, the second password key, the public key, and the secret key to the cells to store the first password key, the second password key, the public key, and the secret key, where the second data is different from the first data, a value of the first password key value and a value of the second password key are prime numbers, and the public key is provided to a host connected to the device.

Nonvolatile memory device storing a public key and a secret key, and an electronic device comprising the same

A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.

Semiconductor device

A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.

A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

Non-volatile memory device and a read method thereof

A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Nonvolatile memory device configured to adjust a read parameter based on degradation level

A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.

Device and method for initializing channel in nonvolatile memory device

A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.

Dynamic power control system for memory device and memory device using the same

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Seongnam-si, South Korea

Dae Seok Byeon