Samsung Electronics Co., Ltd.

Dae-kwon Kang

Jae-Seok Yang

Dong-Gyun Kim

Ji-Young Jung

Sung-Wook Hwang

Sung-Keun Park

Young-Gook Park

According to example embodiments of inventive concepts, a layout design system includes a processor, a storage unit configured to store a layout design, and a stitch module. The layout design includes a first pattern group and a second pattern group disposed in accordance with a design. The first pattern group including a first pattern for patterning at a first time. The second pattern group including a second pattern for patterning at a second time that is different than the first time. The stitch module is configured to detect an iso-pattern of the second pattern using the processor. The stitch module is configured to repetitively designate at least one of the first pattern, which is spaced apart from the iso-pattern by a pitch or more, to the second pattern group using the processor.

Layout design system, system and method for fabricating mask pattern using the same

In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.

Method of decomposing layout of semiconductor device and method of manufacturing semiconductor device using the same

A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

Layout decomposition methods and systems

A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.

Method of decomposing layout of semiconductor device for quadruple patterning technology process and method of manufacturing semiconductor device using the same

Provided are an electronic design automation apparatus and method. The electronic design automation method includes: loading, by a processor, a rule file having limitations on a reference design file; extracting, by the processor, a plurality of unit operations for respectively performing the limitations from the loaded file; and automatically forming, by the processor, a flowchart corresponding to the rule file based on relations between the plurality of unit operations.

Electronic design automation method and apparatus thereof

A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.

Growing community of inventors

Yongin-si, South Korea

Dae-kwon Kang