Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Dae Jung Byun

Jin Won Lee

Jung Soo Kim

Yong Duk Lee

Je Sang Park

Chang Hwa Park

Sang Ho Jeong

Ki Ho Na

Mi Sun Hwang

Sang Hyun Sim

Chang Min Ha

Doo Hwan Lee

Yeo Il Park

Tae Hong Min

Byung Ho Kim

Joo Young Choi

Yoo Rim Cha

Pyung Hwa Han

Jun Hyeong Jang

Ung Hui Shin

Hyoung Joon Kim

Dek Gin Yang

Eun Sil Kim

Yeong A Kim

Tae Ho Ko

Myung Gun Chong

Duck Young Maeng

Kwang Soo Park

A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.

Printed circuit board

A flexible printed circuit board includes a base film; a circuit pattern disposed on one surface of the base film; and a coverlay film covering the circuit pattern. The base film is divided into a flexible area and a rigid area, and the circuit pattern of the flexible area comprises a portion thinner than a portion of the circuit pattern of the rigid area.

Flexible printed circuit board and electronic device including the same

A printed circuit board includes a first insulating layer having a first modulus; a second insulating layer disposed on the first insulating layer and having a second modulus; and a cavity penetrating the second insulating layer, wherein the second modulus is greater than the first modulus, and wherein an edge portion of a bottom surface of the cavity is formed of an insulating material.

Printed circuit board and substrate including electronic component embedded therein

An electronic component embedded substrate includes a core structure including a first insulating body and core wiring layers and having a cavity and having a stopper layer disposed as a bottom surface; an electronic component disposed in the cavity and attached to the stopper layer; and a build-up structure including a second insulating body covering at least a portion each of the core structure and the electronic component and filling at least a portion of the cavity, and build-up wiring layers wherein the stopper layer has a first region in which a portion of one surface is exposed from the first insulating body and a second region in which the other portion of one surface is covered with the first insulating body, and a surface roughness of one surface of the stopper layer in the first region is greater than that of the stopper layer in the second region.

Electronic component embedded substrate

A substrate embedded electronic component package includes a core member having a cavity in which a metal layer is disposed on a bottom surface thereof, an electronic component disposed in the cavity, an encapsulant filling at least a portion of the cavity and covering at least a portion of each of the core member and the electronic component, and a connection structure disposed on the encapsulant and including a first wiring layer connected to the electronic component. A wall surface of the cavity has at least one groove portion protruding outwardly from a center of the cavity, and the groove portion extends to a same depth in the core member as a depth of the cavity.

Substrate embedded electronic component package

A substrate having an electronic component embedded therein includes a core structure including a first insulating body and core wiring layers and having a cavity penetrating through a portion of the first insulating body, an electronic component disposed in the cavity, an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, a wiring layer disposed on the insulating material, and a build-up structure disposed on the insulating material and including a second insulating body and a build-up wiring layer. A material of the first insulating body has a coefficient of thermal expansion (CTE) less than a CTE of the second insulating body, and the insulating material has a CTE less than a CTE of a material of the second insulating body.

Substrate having electronic component embedded therein

A cable substrate includes an insulating layer, a slit portion penetrating through at least a portion of the insulating layer in a thickness direction of the insulating layer, and a dummy pattern disposed on the insulating layer. At least a portion of the dummy pattern is exposed to the slit portion.

Cable substrate

A substrate having an electronic component embedded therein includes a core structure including a first insulating body and a plurality of core wiring layers disposed on or in the first insulating body, and having a cavity penetrating at least a portion of the first insulating body in a thickness direction of the substrate and including a stopper layer as a bottom surface of the cavity, and an electronic component disposed in the cavity and attached to the stopper layer, and a surface of the stopper layer connected to the electronic component has a composite including at least two among a metal material, an inorganic particle, a filler, and an insulating resin.

A substrate having an electronic component embedded therein includes a core structure including a first insulating body and first wiring layers and having a cavity, an electronic component embedded in the cavity, a build-up structure including a second insulating body, covering at least a portion of each of the core structure and the electronic component and filling a portion of the cavity, and second wiring layers, a first passivation layer disposed on a side of the core structure opposing a side of the core structure on which the build-up structure is disposed, and a second passivation layer disposed on a side of the build-up structure opposing a side of the build-up structure on which the core structure is disposed, wherein the first and second passivation layers include different types of materials.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.

A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.

Growing community of inventors

Suwon-si, South Korea

Dae Jung Byun