Samsung Electronics Co., Ltd.

Dae-Joung Kim

Sang-Mun Chon

Kyoung-mi Kim

Kwang-sub Yoon

Jae-ho Kim

Baik-soon Choi

Sang-Kyu Park

Shi-Yong Yi

Seung-Hyun Ahn

Yeu-Young Youn

Eun-Mi Bae

Yong-Woo Lee

In-Sun Park

Jae-Seung Hwang

Hyun-seok Lim

Seok-Hwan Oh

Young-Mi Lee

Min-Chul Chae

Ji-Yong You

Dong-Jo Kang

A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.

Ion implantation mask forming method

A thinner composition includes propylene glycol ether acetate, methyl 2-hydroxy-2-methyl propionate, and an ester compound such as ethyl lactate, ethyl 3-ethoxy propionate or a mixture thereof.

Thinner composition and method of removing photoresist using the same

An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.

Overlay mark and method of forming the same

A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one sidewall of the gate structure. A second metal silicide layer pattern, having a second thickness thinner than the first thickness, is formed on the one or more impurity regions.

Semiconductor device and method of manufacturing the same

In a method for forming a semiconductor device and a semiconductor device having an overlay mark, a first pattern for the semiconductor device is formed in a semiconductor device formation region of a semiconductor substrate and simultaneously in a first mark formation region of the semiconductor substrate. A second pattern for the semiconductor device is formed on a resultant structure in the semiconductor device formation region of the semiconductor substrate and simultaneously in a second mark formation region of the semiconductor substrate. The first and second patterns in the first and second mark formation regions, respectively, are inspected for misalignments using overlay marks formed to have shapes and sizes identical to those of real patterns in the semiconductor device formation region of the semiconductor substrate. By measuring misalignments of real patterns using the overlay marks, overlay mismatch between the semiconductor device formation region and the overlay mark may be prevented.

Method for manufacturing a semiconductor device and semiconductor device with overlay mark

Growing community of inventors

Suwon-si, South Korea

Dae-Joung Kim