Lg Semicon Co., Ltd.

Kookmin University

Samsung Electronics Co., Ltd.

Goldstar, Co., Ltd.

Cheil Synthetics Inc.

Dae Jeong Kim

Hyun Sun Mo

Min Su Kim

Young Jin Kim

Dae Hwan Kim

Young Rag Do

Won Jae Shin

Hyung Min Kim

Yong Kim

Kwang Woo Lee

Dae W Ihm

Seong Jin Choi

Nam Hyung Kim

Chang Min Lee

Gu Min Jeong

Il Gyu Jung

Yong Jun Yu

Heon Gwon Lee

In Su Choi

Sung Ho Wang

Do Han Kim

Youn-Cherl Shin

Chang S Lee

Deok Ho Seo

In Ho Cho

Kab Yong Kim

Myung S Lee

In Hwan Jung

Hyunsun Mo

Dong Myung Kim

Sun Woong Choi

Sung Yeon Jang

Sanggyu Yim

An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Semiconductor device and electronic device including the same

Disclosed is a bio illuminance measuring apparatus including a circadian lambda filter passing external light along according to a circadian rhythm sensitivity curve, a visual lambda filter passing the external light along according to a visual sensitivity curve, a photo sensing portion sensing and converting the external light, which has passed through the circadian lambda filter, into a circadian wavelength signal and sensing and converting the external light, which has passed through the visual lambda filter, into a visual wavelength signal, and an illuminance calculating portion which calculates a ratio between the circadian wavelength signal and the visual wavelength signal, calculates a circadian action factor by applying the ratio between the circadian wavelength signal and the visual wavelength signal to a circadian action function which varies according to the visual wavelength signal, and calculates a bio illuminance value of the external light on the basis of the circadian action factor.

Bio illuminance measuring device for determining circadian action

Disclosed are an apparatus and a system for managing circadian rhythm. The apparatus includes an illuminance measuring portion which measures a bio illuminance value of external light using a circadian lambda filter which passes the external light along according to a circadian rhythm sensitivity curve and a visual lambda filter which passes the external light along according to a visual sensitivity curve, a controller which outputs a control signal for reinforcing a user's circadian rhythm on the basis of the bio illuminance value, and a circadian rhythm reinforcing portion which emits light of a circadian wavelength band toward the user according to the control signal.

Circadian rhythm management apparatus and system

A clock generator including a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal, a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal, and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal is provided.

Clock generator

A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Semiconductor memory device and refresh method thereof

A pulse generating circuit for a dynamic random access memory includes a fixed pulse generating unit receiving an input signal and generating an output pulse signal of a fixed width, a pulse delay unit receiving the input signal and delaying an output pulse signal of a variable width, a pulse width detecting unit receiving the input signal and an inverted input signa, outputting a first flag signal displaying a low pulse width by detecting the low pulse width of the input signal, and outputting a second flag signal displaying a high pulse width by detecting the high pulse width of the input signal, a NOR gate performing a logical operation on the first flag signal and the second flag signal and outputting a third flag signal, and a multiplexer coupled to the fixed pulse generating unit, the pulse delay unit, and the pulse width detecting unit and outputting an output pulse signal in accordance with the third flag signal.

Pulse generating circuit for dynamic random access memory device

An improved current detection start-up circuit for a reference voltage circuit which restarts a reference voltage circuit when a reference voltage drops by a predetermined level, i.e., turns off, due to noise or a variation of a system voltage. The circuit includes: a current detection circuit for detecting the current being applied to a reference voltage circuit; and a start-up circuit for starting the reference voltage circuit when the current detected by the current detection circuit is below a predetermined level.

Current detection start-up circuit for reference voltage circuit

A digital delay locked loop (DLL) includes a phase detector for outputting a comparing signal by comparing a system clock signal with a chip clock signal, a shift register for sequentially shifting data bit values in both the directions in accordance with the comparing signal, a phase delay unit for delaying and outputting the system clock signal in accordance with each bit value of the shift register, a domain selecting controller for detecting an overflow or an underflow condition of the shift register and outputting a domain selection controlling signal, and a domain selector for adjusting the phase of a driving signal from one region comprising 0.degree..about.180.degree. and to another area comprising 180.degree..about.360.degree. and carrying out a domain transition whenever an overflow or an underflow condition is generated when the phase reaches a boundary region of the two domains.

Phase delay correction apparatus

A circuit for detecting leakage voltage of a MOS capacitor, the detecting circuit including a timing control signal generator for generating a timing control signal; a sample/hold circuit for sampling and holding a first voltage, the sample/hold circuit comprising a switching circuit switched by an output of the timing control signal generator and being operatively coupled to a MOS capacitor; a monitoring capacitor for monitoring a leakage voltage of the MOS capacitor operatively coupled to the sample/hold circuit; a monitoring capacitor precharge circuit for holding a second voltage in the monitoring capacitor; and a leakage voltage detecting portion for detecting when a leakage voltage of the monitoring capacitor is below a predetermined value. The leakage voltage detecting portion is also capable of detecting what value the leakage voltage of the monitoring capacitor is, for example, when the leakage voltage is below the predetermined value.

Circuit for detecting leakage voltage of MOS capacitor

An improved delay characteristic compensation circuit for a memory device which is capable of constantly maintaining the characteristic of the delay path by connecting or disconnecting the delay devices to the delay path by detecting quickly the variation of the supply voltage, which includes a signal delay unit for sequentially delaying an input signal; a voltage variation detector for detecting a variation of a digital supply voltage and adjusting the level of a divide voltage with respect to the supply voltage at a predetermined ratio; a code data generator for generating a code data in accordance with the voltage adjusted by the voltage variation detector; and a delay characteristic compensation unit for connecting a predetermined number of delay devices to a delay path of the delay unit in accordance with a code data generated by the code data generator for dividing the same so as to constantly maintain the delay characteristic of the delay unit.

Delay characteristic compensation circuit for memory device

A method of reproducing a video signal in a digital video cassette recorder, comprising the step of performing intra-frame coding at an interval of a predetermined number of frames of the video signal to compress the video signal and recording the compressed video signal on a video tape, and the step of varying a travelling speed of the video tape according to a desired one of normal, still, fast forward, fast reverse, slow forward and slow reverse playback modes to reproduce the video signal recorded on the video tape in the desired playback mode. The travelling speed of the video tape is varied by combining speeds of the normal, still, fast forward jump and fast reverse jump modes according to the desired playback mode. The intra-frame coding is performed at an interval of L frames, where L is a natural number greater than or equal to 2, and first slice data of the coded Lth frame becomes first video data of a transmitted data field. Therefore, editing and speed change modes of the digital video cassette recorder can be performed in the basic unit of the coded Lth frame.

Method of multi-speed recording-reproducing a video signal in digital

There is disclosed a method for the production of aliphatic copolyester film. The method comprises the steps of: applying esterification or ester-interchange to a reaction mixture of at least one acid component selected from the group consisting of succinic acid, succinic anhydride and succinic acid ester, 1,4-butanediol as a main diol component, 2,2-dimethyl-1,3-propanediol of 1 to 30% by mole based on the mole of the acid component, multifunctional compound 0.01 to 1% by mole, based on the mole of the acid component, multifunctional compound have more than three functional group of hydroxy group or carboxy group at below 220.degree. C., so as to give an oligomer mixture; polycondensing the oligomer into an aliphatic copolyester at a temperature of 240.degree. to 260.degree. C. under reduced pressures of not more than 1 mmHg in the presence of a catalyst; and melt-extruding the aliphatic copolyester using T die. Improved in draw ratio, the aliphatic copolyester film provided by the method can be applied to various applications, such as films, bottles, glass fiber-reinforced plastics, adhesives, paints.

Method for the production of aliphatic copolyester film

Growing community of inventors

Seoul, South Korea

Dae Jeong Kim