Samsung Electronics Co., Ltd.

Dae-Je Jin

Dong-Sun Min

Tae-young Jeong

Kwang-Byeog Seo

Chang-Hyun Kim

Jun-Young Jeon

Su-In Cho

A semiconductor memory device, having cells respectively therein given information through rewriting, i.e., a refreshing operation, capable of performing non-periodic refreshing operations is disclosed. The semiconductor memory element internally includes a refresh request signal generator having a reference memory cell 51 connected to a word line in the memory device. The refresh request signal generator 100A generates refresh request signals only at that moment of erasing of information stored in the memory cell. The outputted refresh request signals cause refresh signals to transfer to the memory cell. Thus, non-periodic refreshing operations can be performed, thereby reducing the power consumption, and increasing the number of data input/output work.

Semiconductor memory device capable of executing non-periodic refreshing

A manufacturing method for a DRAM cell provided with a stacked capacitor is disclosed. The method including: (1) defining a switching transistor region by forming a field oxide layer upon a first conduction type semiconductor substrate; (2) forming source and drain regions of a second conduction type; (3) forming respective first conductive layers on a part of said field oxide layer and on a gate oxide layer over a channel region within the switching transistor region; and forming a first insulating layer; (4) forming a second conductive layer and removing parts of the second conductive layer which are over the channel region and the drain region; (5) forming an opening for exposing a part of the source region; (6) forming a third conductive layer on the substrate and overlapping the remaining portions of the second conductive layer, to provide a portion thereof having a saddle structure providing a gentle slope; (7) etching to remove portions of the second and third conductive layers; (8) forming a dielectric layer; and (9) forming a fourth conductive layer.

Stacked capacitor dynamic random access memory with a sloped lower

Manufacturing method for a DRAM cell

The higher packing cells memory circuit includes a plurality word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers by, for example, arranging word lines in a group to provide a cross-over or to twist the word line is not continuously adjacent to the same neighboring word line, so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

Method for reducing coupling noise of word lines in a semiconductor

A supply voltage converter circuit for use in reduced geometry high-density semiconductor memory devices, capable of reducing current consumption to as small a value as possible and achieving high-speed operation. The circuit includes a reference voltage generator, for generating a constant reference voltage, and a peripheral power-supply circuit, and array power-supply circuit for providing the internal supply voltage to the peripheral and array circuits, respectively. Each of the peripheral and array power circuits includes a divider, generating a voltage proportional to said internal supply voltage; a main power-supplying part including a main differential amplifier which compares the proportional voltage with said reference voltage and is activated by a given pulse, and a main power component providing the internal source supply voltage in response to output signal of the main differential amplifier; and a sub power supply part including a sub differential amplifier comparing the proportional voltage with the reference voltage, the differential amplifier being at a constant activation state, and a sub power component providing the internal source supply voltage in response to output signal of the sub differential amplifier.

Supply voltage converter for high-density semiconductor memory device

A method of forming low-resistive contact to at least two preohmic regions formed in a silicon substrate having a thick insulating layer thereon, including the steps of depositing a polysilicon on the insulating layer, performing an anisotropic etch for opening the preohmic regions, sputter-depositing a titanium deposit, the deposited titanium having electrical disconnections on the vertical side-walls of the opening regions, siliciding the titanium deposit, and depositing a metal silicide deposit for preventing electrical disconnections. Another embodiment uses a sputter-deposited titanium silicide deposit instead of titanium silicide. Still another embodiment includes the step of forming holes by an anisotropic etch, depositing polysilicon in the holes and on the insulating layer, sputter-depositing an titanium deposit, forming an titanium silicide deposit, and depositing a metal silicide deposit.

Growing community of inventors

Seoul, South Korea

Dae-Je Jin