Samsung Electronics Co., Ltd.

Dae-Hyun Jang

Kyoung-Sub Shin

Seong-Soo Lee

Jung-Ik Oh

Yoo-Chul Kong

Yong-Woo Lee

Jae-Seung Hwang

Ji-young Lee

Gyung-Jin Min

Jong-hyuk Kim

Suk-Ho Joo

Seung-Hyun Moon

Yong-Hyun Kwon

Han-Na Cho

Jin-Hyuk Yoo

Han-Geun Yu

According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

Method of fabricating semiconductor devices having vertical cells

Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

Semiconductor device

A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

Method of forming a step pattern structure

According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Methods of manufacturing a vertical type semiconductor device

A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Methods of manufacturing a semiconductor device and a semiconductor memory device thereby

A self-align patterning method for forming patterns includes forming a first layer on a substrate, forming a plurality of first hard mask patterns on the first layer, forming a sacrificial layer on top surfaces and sidewalls of the first hard mask patterns, thereby forming a gap between respective facing portions of the sacrificial layer on the sidewalls of the first hard mask patterns, forming a second hard mask pattern in the gap, etching the sacrificial layer using the second hard mask pattern as a mask to expose the first hard mask patterns, exposing the first layer using the exposed first hard mask patterns and the second hard mask pattern, and etching the exposed first layer using the first and second hard mask patterns.

Method of forming pad patterns using self-align double patterning method, pad pattern layout formed using the same, and method of forming contact holes using self-align double patterning method

Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask. The metal wiring having at least one metal layer pattern and at least one barrier metal layer pattern may be formed on the substrate by etching the at least one barrier metal layer and the at least one metal layer using the hard mask pattern as an etching mask. The metal wiring having a reduced width may be obtained without a failure (e.g., a bridge).

Growing community of inventors

Seongnam-si, South Korea

Dae-Hyun Jang