Samsung Electronics Co., Ltd.

Dae-hyun Jang

Jong-hyuk Kim

Seung-hyun Moon

Kyoung-Sub Shin

Jung-Ik Oh

Ha-Na Kim

Yong-Ho Jeon

Sun-ki Min

Yoo-Chul Kong

Jin-Hyuk Yoo

Seung-Seok Ha

Young-ju Park

A display apparatus includes a display, a single physical button and a processor configured to control the display to display a guide user interface (UI), a selection UI and a plurality of menu items, based on a user input received via the single physical button being identified as a short click input, move the selection UI from one menu item among the plurality of menu items to another menu item among the plurality of menu items, based on the user input being identified as a long press input, select the one menu item and execute a control function corresponding to the selected one menu item, and based on an execution of the control function, control the display to display a setting UI indicating a current setting value of the control function.

Display apparatus for performing function of user selected menu item on a user interface and method for controlling display apparatus

A display device is provided. The display apparatus includes: a display configured to display a user interface screen; an input interface configured to receive a user operation to select and execute at least one menu item included in the user interface screen; and a processor configured to separately recognize a short click and a long press based on an input time of the user operation, constantly maintain an execution speed of a function corresponding to a selected menu item within a preset critical time in the time for which the input of the long press is continued and accelerate the execution speed of the corresponding function after the preset critical time passes.

Display apparatus for selecting and executing menu items on a user interface, and controlling method thereof

A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings.

Method of manufacturing semiconductor device to prevent defects

Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

Semiconductor device

A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.

Vertical memory devices and methods of manufacturing the same

According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

Growing community of inventors

Suwon-si, South Korea

Dae-hyun Jang