Samsung Electronics Co., Ltd.

Dae-Hyun Chung

Seung-Jun Bae

Sang-woong Shin

Jin-gook Kim

Kyu-Hyoun Kim

Woo-Jin Lee

Ho-young Song

Si-Hong Kim

Kwang-II Park

Kyo-hyoun Kim

An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.

AC-coupling phase interpolator and delay-locked loop using the same

A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input pad of the semiconductor chip and the first ground voltage terminal being electrically coupled to the first ground voltage pad of the semiconductor chip, a capacitor and a resistor that are coupled between the signal input terminal and the first ground voltage terminal, and a first inductor realized by coupling the signal input terminal and the signal input pad.

Semiconductor device and signal terminating method thereof

A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.

Level shifter of semiconductor device and method for controlling duty ratio in the device

A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device.

Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof

A delay locked loop (DLL) is provided that includes a phase detector configured to detect a phase error between an internal clock signal and the external clock signal and output a phase error signal. A low pass filter is configured to output a predetermined control signal in response to the phase error signal. A variable delay circuit is configured to change a delay time in response to the predetermined control signal, delay the phase of the external clock signal with respect to the changed delay time, lock the delayed external clock signal and output the internal clock signal. A compensation delay circuit is configured to receive a control voltage based on a delay time introduced by a data output circuit and delay a phase of the internal clock signal for a first delay time based on the control voltage and output the delayed internal clock signal to the phase detector. Methods of compensating a delay for a DLL are also provided.

Delay locked loops having delay time compensation and methods for compensating for delay time of the delay locked loops

Disclosed is a delay locked-loop circuit comprising a phase detector for detecting a phase difference between an external clock signal and an internal clock signal, a delay unit controller for generating a control signal in response to output of the phase detector, and a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising a first group of delay cells used at or above a predetermined frequency, a second group of delay cells used with the first group of delay cells at or below a predetermined frequency, switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal, and a switch for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cells in the first group.

Delay locked-loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably

A synchronous semiconductor memory device includes an output control signal generating circuit that generates a data output control signal in response to an internal clock signal, an output control clock signal and a CAS latency signal. The output control signal generating circuit successively shifts read information signals in response to the internal clock signal and the output control clock signal, both source clocks of which are identical, and generates one of the shifted read information signals as an output control signal for indicating a data output period in response to the CAS latency signal. The synchronous semiconductor memory device can synchronize the source clocks of the clock signals used in the output control signal generating circuit thereby reducing the influence of clock jitter.

Methods for generating output control signals in synchronous semiconductor memory devices and related semiconductor memory devices

A delay circuit has an input node receives an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.

Pulsed signal transition delay adjusting circuit

Synchronous semiconductor memory devices and methods of operating are provided. The device has a latency N and includes a memory cell array, a stack unit having N storage units and a frequency detector that provides an output signal based on the relationship of the frequency of operation clock to a predetermined frequency. A control circuit controls the stack unit in response to the output signal of the frequency detector. The control circuit latches data read from the memory and controls the stack unit so that the latched data is stored from a clock cycle when a read command is sent until an N-th cycle afterwards if the clock frequency is greater than the predetermined frequency and delays the latched data for one cycle and controls the stack unit so that the delayed data is stored from one cycle after the read command is sent until an N&plus;1 cycle afterwards.

Growing community of inventors

Yongin, South Korea

Dae-Hyun Chung