Samsung Electronics Co., Ltd.

Korea Institute of Science and Technology

Seoul National University

Dae-Hwan Kang

Gwan-Hyeob Koh

Ji-Hyun Jeong

Kyu-Rie Sim

Jin-Woo Lee

Won Mok Kim

Taek Sung Lee

Jeung-hyun Jeong

In Ho Kim

Masayuki Terai

Byung-ki Cheong

Il-mok Park

Kyeong Seok Lee

Ki-bum Kim

Chang-Wook Jeong

Hyeong-jun Kim

Kwang-woo Lee

Seung-Pil Ko

Du-Eung Kim

Kwang-Jin Lee

Ki Bum Kim

Tae-Yon Lee

Jae-kyu Lee

Young-Nam Hwang

Dong-Won Lim

Byung Ki Cheong

Chang-yong Um

In-Ho Kim

Song-yi Kim

Jae-Min Shin

Dong-Ho Ahn

Dong Ho Anh

Han Ju Jung

Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

Memory cell and memory device comprising selection device layer, middle electrode layer and variable resistance layer

A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

Memory device and method of manufacturing the same

The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.

Memory device and electronic apparatus including the same

A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.

Memory devices having crosspoint memory arrays therein with multi-level word line and bit line structures

The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.

Semiconductor devices and methods of manufacturing the same

A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.

Variable resistance memory devices and methods of manufacturing the same

A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.

A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction.

The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.

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Seoul, South Korea

Dae-Hwan Kang